Rick Chen 52923c6db7 riscv: cache: Implement i/dcache [status, enable, disable] ...

AndeStar RISC-V(V5) provide mcache_ctl register which
can configure I/D cache as enabled or disabled.

This CSR will be encapsulated by CONFIG_RISCV_NDS.
If you want to configure cache on AndeStar V5
AE350 platform. YOu can enable [*] AndeStar V5 ISA support
by make menuconfig.

This approach also provide the expansion when the
vender specific features are going to join in.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>

2018-11-26 13:58:01 +08:00

..

ax25

riscv: cache: Implement i/dcache [status, enable, disable]

2018-11-26 13:58:01 +08:00

qemu

riscv: cache: Implement i/dcache [status, enable, disable]

2018-11-26 13:58:01 +08:00

cpu.c

riscv: save hart ID and device tree passed by prior boot stage

2018-11-26 13:57:32 +08:00

Makefile

riscv: Make start.S available for all targets

2018-10-03 17:48:14 +08:00

start.S

riscv: cache: Implement i/dcache [status, enable, disable]

2018-11-26 13:58:01 +08:00

u-boot.lds

riscv: Make start.S available for all targets

2018-10-03 17:48:14 +08:00