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9b9c6516b0
Move arch/arm/include/asm/arch-zynq/* -> arch/arm/mach-zynq/include/mach/* Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
77 lines
2.5 KiB
C
77 lines
2.5 KiB
C
/*
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* Copyright (c) 2013 Xilinx, Inc.
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* Copyright (c) 2015 DAVE Embedded Systems
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ZYNQ_GPIO_H
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#define _ZYNQ_GPIO_H
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#define ZYNQ_GPIO_BASE_ADDRESS 0xE000A000
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/* Maximum banks */
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#define ZYNQ_GPIO_MAX_BANK 4
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#define ZYNQ_GPIO_BANK0_NGPIO 32
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#define ZYNQ_GPIO_BANK1_NGPIO 22
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#define ZYNQ_GPIO_BANK2_NGPIO 32
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#define ZYNQ_GPIO_BANK3_NGPIO 32
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#define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
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ZYNQ_GPIO_BANK1_NGPIO + \
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ZYNQ_GPIO_BANK2_NGPIO + \
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ZYNQ_GPIO_BANK3_NGPIO)
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#define ZYNQ_GPIO_BANK0_PIN_MIN 0
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#define ZYNQ_GPIO_BANK0_PIN_MAX (ZYNQ_GPIO_BANK0_PIN_MIN + \
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ZYNQ_GPIO_BANK0_NGPIO - 1)
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#define ZYNQ_GPIO_BANK1_PIN_MIN (ZYNQ_GPIO_BANK0_PIN_MAX + 1)
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#define ZYNQ_GPIO_BANK1_PIN_MAX (ZYNQ_GPIO_BANK1_PIN_MIN + \
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ZYNQ_GPIO_BANK1_NGPIO - 1)
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#define ZYNQ_GPIO_BANK2_PIN_MIN (ZYNQ_GPIO_BANK1_PIN_MAX + 1)
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#define ZYNQ_GPIO_BANK2_PIN_MAX (ZYNQ_GPIO_BANK2_PIN_MIN + \
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ZYNQ_GPIO_BANK2_NGPIO - 1)
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#define ZYNQ_GPIO_BANK3_PIN_MIN (ZYNQ_GPIO_BANK2_PIN_MAX + 1)
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#define ZYNQ_GPIO_BANK3_PIN_MAX (ZYNQ_GPIO_BANK3_PIN_MIN + \
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ZYNQ_GPIO_BANK3_NGPIO - 1)
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/* Register offsets for the GPIO device */
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/* LSW Mask & Data -WO */
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#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
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/* MSW Mask & Data -WO */
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#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
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/* Data Register-RW */
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#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
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/* Direction mode reg-RW */
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#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
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/* Output enable reg-RW */
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#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
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/* Interrupt mask reg-RO */
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#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
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/* Interrupt enable reg-WO */
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#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
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/* Interrupt disable reg-WO */
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#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
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/* Interrupt status reg-RO */
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#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
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/* Interrupt type reg-RW */
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#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
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/* Interrupt polarity reg-RW */
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#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
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/* Interrupt on any, reg-RW */
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#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
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/* Disable all interrupts mask */
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#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
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/* Mid pin number of a bank */
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#define ZYNQ_GPIO_MID_PIN_NUM 16
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/* GPIO upper 16 bit mask */
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#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
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#define BIT(x) (1<<x)
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#endif /* _ZYNQ_GPIO_H */
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