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1b8fec1393
APM821XX is a new line of SoCs which are derivatives of PPC44X family of processors. This patch adds support of CPU, cache, tlb, 32k ocm, bootstraps, PLB and AHB bus. Signed-off-by: Tirumala R Marri <tmarri@apm.com> Signed-off-by: Stefan Roese <sr@denx.de>
73 lines
2.7 KiB
C
73 lines
2.7 KiB
C
/*
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* Copyright (c) 2010, Applied Micro Circuits Corporation
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* Author: Tirumala R Marri <tmarri@apm.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _APM821XX_H_
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#define _APM821XX_H_
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#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */
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/* Memory mapped registers */
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#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
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#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
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#define SDR0_SRST0_DMC 0x00200000
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#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */
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/* AHB config. */
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#define AHB_TOP 0xA4
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#define AHB_BOT 0xA5
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/* clk divisors */
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#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */
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#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */
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#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */
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#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */
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#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */
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#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */
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#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000/* PLB Early Clk Div*/
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#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */
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#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */
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/*
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+ * Clocking Controller
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+ */
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#define CPR0_CLKUPD 0x0020
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#define CPR0_PLLC 0x0040
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#define CPR0_PLLC_SEL(pllc) (((pllc) & 0x01000000) >> 24)
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#define CPR0_PLLD 0x0060
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#define CPR0_PLLD_FDV(plld) (((plld) & 0xff000000) >> 24)
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#define CPR0_PLLD_FWDVA(plld) (((plld) & 0x000f0000) >> 16)
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#define CPR0_CPUD 0x0080
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#define CPR0_CPUD_CPUDV(cpud) (((cpud) & 0x07000000) >> 24)
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#define CPR0_PLB2D 0x00a0
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#define CPR0_PLB2D_PLB2DV(plb2d) (((plb2d) & 0x06000000) >> 25)
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#define CPR0_OPBD 0x00c0
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#define CPR0_OPBD_OPBDV(opbd) (((opbd) & 0x03000000) >> 24)
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#define CPR0_PERD 0x00e0
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#define CPR0_PERD_PERDV(perd) (((perd) & 0x03000000) >> 24)
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#define CPR0_DDR2D 0x0100
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#define CPR0_DDR2D_DDR2DV(ddr2d) (((ddr2d) & 0x06000000) >> 25)
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#define CLK_ICFG 0x0140
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#endif /* _APM821XX_H_ */
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