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1a28852467
Add support for a bunch of new clocks, including PCIe, GENI (for all peripherals used on the RB3 Gen 2), and some missing USB clocks. Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250314-sc7280-more-clocks-v1-3-ead54487c38e@linaro.org Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
229 lines
7.3 KiB
C
229 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Clock drivers for Qualcomm sc7280
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*
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* (C) Copyright 2024 Linaro Ltd.
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*/
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#include <linux/types.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <linux/bug.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/qcom,gcc-sc7280.h>
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#include "clock-qcom.h"
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#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020
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#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038
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#define USB30_SEC_MASTER_CLK_CMD_RCGR 0x9e020
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#define USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR 0x9e038
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#define PCIE_1_AUX_CLK_CMD_RCGR 0x8d058
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#define PCIE1_PHY_RCHNG_CMD_RCGR 0x8d03c
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#define PCIE_1_PIPE_CLK_PHY_MUX 0x8d054
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static const struct freq_tbl ftbl_gcc_usb30_prim_master_clk_src[] = {
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F(66666667, CFG_CLK_SRC_GPLL0_EVEN, 4.5, 0, 0),
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F(133333333, CFG_CLK_SRC_GPLL0, 4.5, 0, 0),
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F(200000000, CFG_CLK_SRC_GPLL0_ODD, 1, 0, 0),
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F(240000000, CFG_CLK_SRC_GPLL0, 2.5, 0, 0),
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{ }
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};
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static const struct freq_tbl ftbl_gcc_usb30_sec_master_clk_src[] = {
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F(60000000, CFG_CLK_SRC_GPLL0_EVEN, 5, 0, 0),
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F(120000000, CFG_CLK_SRC_GPLL0_EVEN, 2.5, 0, 0),
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{ }
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};
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static ulong sc7280_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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const struct freq_tbl *freq;
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if (clk->id < priv->data->num_clks)
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debug("%s: %s, requested rate=%ld\n", __func__, priv->data->clks[clk->id].name, rate);
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switch (clk->id) {
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case GCC_USB30_PRIM_MASTER_CLK:
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freq = qcom_find_freq(ftbl_gcc_usb30_prim_master_clk_src, rate);
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clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
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freq->pre_div, freq->m, freq->n, freq->src, 8);
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return freq->freq;
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case GCC_USB30_PRIM_MOCK_UTMI_CLK:
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clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
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return 19200000;
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case GCC_USB3_PRIM_PHY_AUX_CLK_SRC:
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clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
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return 19200000;
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case GCC_USB30_SEC_MASTER_CLK:
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freq = qcom_find_freq(ftbl_gcc_usb30_sec_master_clk_src, rate);
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clk_rcg_set_rate_mnd(priv->base, USB30_SEC_MASTER_CLK_CMD_RCGR,
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freq->pre_div, freq->m, freq->n, freq->src, 8);
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return freq->freq;
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case GCC_USB30_SEC_MOCK_UTMI_CLK:
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clk_rcg_set_rate(priv->base, USB30_SEC_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
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return 19200000;
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case GCC_USB3_SEC_PHY_AUX_CLK_SRC:
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clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 1, 0);
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return 19200000;
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case GCC_PCIE1_PHY_RCHNG_CLK:
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clk_rcg_set_rate(priv->base, PCIE1_PHY_RCHNG_CMD_RCGR, 5, CFG_CLK_SRC_GPLL0_EVEN);
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return 100000000;
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default:
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return rate;
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}
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}
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static const struct gate_clk sc7280_clks[] = {
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GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0xf07c, 1),
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GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0xf010, 1),
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GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0xf080, 1),
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GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0xf018, 1),
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GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0xf01c, 1),
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GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0xf054, 1),
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GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0xf058, 1),
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GATE_CLK(GCC_CFG_NOC_USB3_SEC_AXI_CLK, 0x9e07c, 1),
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GATE_CLK(GCC_USB30_SEC_MASTER_CLK, 0x9e010, 1),
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GATE_CLK(GCC_AGGRE_USB3_SEC_AXI_CLK, 0x9e080, 1),
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GATE_CLK(GCC_USB30_SEC_SLEEP_CLK, 0x9e018, 1),
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GATE_CLK(GCC_USB30_SEC_MOCK_UTMI_CLK, 0x9e01c, 1),
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GATE_CLK(GCC_USB3_SEC_PHY_AUX_CLK, 0x9e054, 1),
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GATE_CLK(GCC_USB3_SEC_PHY_COM_AUX_CLK, 0x9e058, 1),
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GATE_CLK(GCC_PCIE_CLKREF_EN, 0x8c004, 1),
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GATE_CLK(GCC_PCIE_1_PIPE_CLK, 0x52000, BIT(30)),
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GATE_CLK(GCC_PCIE_1_AUX_CLK, 0x52000, BIT(29)),
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GATE_CLK(GCC_PCIE_1_CFG_AHB_CLK, 0x52000, BIT(28)),
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GATE_CLK(GCC_PCIE_1_MSTR_AXI_CLK, 0x52000, BIT(27)),
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GATE_CLK(GCC_PCIE_1_SLV_AXI_CLK, 0x52000, BIT(26)),
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GATE_CLK(GCC_PCIE_1_SLV_Q2A_AXI_CLK, 0x52000, BIT(25)),
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GATE_CLK(GCC_PCIE1_PHY_RCHNG_CLK, 0x52000, BIT(23)),
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GATE_CLK(GCC_DDRSS_PCIE_SF_CLK, 0x52000, BIT(19)),
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GATE_CLK(GCC_AGGRE_NOC_PCIE_TBU_CLK, 0x52000, BIT(18)),
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GATE_CLK(GCC_AGGRE_NOC_PCIE_1_AXI_CLK, 0x52000, BIT(11)),
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GATE_CLK(GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK, 0x52008, BIT(28)),
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GATE_CLK(GCC_QUPV3_WRAP0_S0_CLK, 0x52008, BIT(10)),
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GATE_CLK(GCC_QUPV3_WRAP0_S1_CLK, 0x52008, BIT(11)),
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GATE_CLK(GCC_QUPV3_WRAP0_S3_CLK, 0x52008, BIT(13)),
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};
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static int sc7280_enable(struct clk *clk)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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if (priv->data->num_clks <= clk->id) {
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debug("%s: unknown clk id %lu\n", __func__, clk->id);
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return 0;
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}
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debug("%s: clk %ld: %s\n", __func__, clk->id, sc7280_clks[clk->id].name);
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switch (clk->id) {
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case GCC_AGGRE_USB3_PRIM_AXI_CLK:
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qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
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fallthrough;
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case GCC_USB30_PRIM_MASTER_CLK:
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qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
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qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
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break;
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case GCC_AGGRE_USB3_SEC_AXI_CLK:
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qcom_gate_clk_en(priv, GCC_USB30_SEC_MASTER_CLK);
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fallthrough;
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case GCC_USB30_SEC_MASTER_CLK:
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qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_AUX_CLK);
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qcom_gate_clk_en(priv, GCC_USB3_SEC_PHY_COM_AUX_CLK);
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break;
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case GCC_PCIE_1_PIPE_CLK:
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clk_phy_mux_enable(priv->base, PCIE_1_PIPE_CLK_PHY_MUX, true);
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break;
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case GCC_PCIE_1_AUX_CLK:
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clk_rcg_set_rate_mnd(priv->base, PCIE_1_AUX_CLK_CMD_RCGR, 1, 0, 0,
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CFG_CLK_SRC_CXO, 16);
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break;
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case GCC_QUPV3_WRAP0_S0_CLK:
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clk_rcg_set_rate_mnd(priv->base, 0x17010, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
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break;
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case GCC_QUPV3_WRAP0_S1_CLK:
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clk_rcg_set_rate_mnd(priv->base, 0x17140, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
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break;
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case GCC_QUPV3_WRAP0_S3_CLK:
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clk_rcg_set_rate_mnd(priv->base, 0x173a0, 1, 0, 0, CFG_CLK_SRC_CXO, 16);
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break;
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}
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return qcom_gate_clk_en(priv, clk->id);
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}
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static const struct qcom_reset_map sc7280_gcc_resets[] = {
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[GCC_PCIE_0_BCR] = { 0x6b000 },
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[GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
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[GCC_PCIE_1_BCR] = { 0x8d000 },
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[GCC_PCIE_1_PHY_BCR] = { 0x8e01c },
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[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
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[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
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[GCC_SDCC1_BCR] = { 0x75000 },
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[GCC_SDCC2_BCR] = { 0x14000 },
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[GCC_SDCC4_BCR] = { 0x16000 },
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[GCC_UFS_PHY_BCR] = { 0x77000 },
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[GCC_USB30_PRIM_BCR] = { 0xf000 },
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[GCC_USB30_SEC_BCR] = { 0x9e000 },
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[GCC_USB3_DP_PHY_PRIM_BCR] = { 0x50008 },
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[GCC_USB3_PHY_PRIM_BCR] = { 0x50000 },
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[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
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[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
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};
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static const struct qcom_power_map sc7280_gdscs[] = {
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[GCC_UFS_PHY_GDSC] = { 0x77004 },
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[GCC_USB30_PRIM_GDSC] = { 0xf004 },
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[GCC_USB30_SEC_GDSC] = { 0x9e004 },
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[GCC_PCIE_1_GDSC] = { 0x8d004 },
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};
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static const phys_addr_t sc7280_rcg_addrs[] = {
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0x10f020, // USB30_PRIM_MASTER_CLK_CMD_RCGR
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0x10f038, // USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR
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0x18d058, // PCIE_1_AUX_CLK_CMD_RCGR
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};
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static const char *const sc7280_rcg_names[] = {
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"USB30_PRIM_MASTER_CLK_SRC",
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"USB30_PRIM_MOCK_UTMI_CLK_SRC",
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"GCC_PCIE_1_AUX_CLK_SRC",
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};
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static struct msm_clk_data qcs404_gcc_data = {
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.resets = sc7280_gcc_resets,
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.num_resets = ARRAY_SIZE(sc7280_gcc_resets),
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.clks = sc7280_clks,
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.num_clks = ARRAY_SIZE(sc7280_clks),
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.power_domains = sc7280_gdscs,
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.num_power_domains = ARRAY_SIZE(sc7280_gdscs),
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.enable = sc7280_enable,
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.set_rate = sc7280_set_rate,
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.dbg_rcg_addrs = sc7280_rcg_addrs,
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.num_rcgs = ARRAY_SIZE(sc7280_rcg_addrs),
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.dbg_rcg_names = sc7280_rcg_names,
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};
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static const struct udevice_id gcc_sc7280_of_match[] = {
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{
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.compatible = "qcom,gcc-sc7280",
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.data = (ulong)&qcs404_gcc_data,
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},
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{ }
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};
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U_BOOT_DRIVER(gcc_sc7280) = {
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.name = "gcc_sc7280",
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.id = UCLASS_NOP,
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.of_match = gcc_sc7280_of_match,
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.bind = qcom_cc_bind,
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.flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
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};
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