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This driver can control up to 32 clocks. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
/*
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* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
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*
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* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DT_BINDINGS_CLOCK_BCM63268_H
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#define __DT_BINDINGS_CLOCK_BCM63268_H
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#define BCM63268_CLK_GLESS 0
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#define BCM63268_CLK_VDSL_QPROC 1
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#define BCM63268_CLK_VDSL_AFE 2
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#define BCM63268_CLK_VDSL 3
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#define BCM63268_CLK_MIPS 4
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#define BCM63268_CLK_WLAN_OCP 5
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#define BCM63268_CLK_DECT 6
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#define BCM63268_CLK_FAP0 7
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#define BCM63268_CLK_FAP1 8
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#define BCM63268_CLK_SAR 9
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#define BCM63268_CLK_ROBOSW 10
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#define BCM63268_CLK_PCM 11
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#define BCM63268_CLK_USBD 12
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#define BCM63268_CLK_USBH 13
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#define BCM63268_CLK_IPSEC 14
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#define BCM63268_CLK_SPI 15
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#define BCM63268_CLK_HSSPI 16
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#define BCM63268_CLK_PCIE 17
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#define BCM63268_CLK_PHYMIPS 18
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#define BCM63268_CLK_GMAC 19
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#define BCM63268_CLK_NAND 20
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#define BCM63268_CLK_TBUS 27
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#define BCM63268_CLK_ROBOSW250 31
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#define BCM63268_TCLK_EPHY1 0
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#define BCM63268_TCLK_EPHY2 1
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#define BCM63268_TCLK_EPHY3 2
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#define BCM63268_TCLK_GPHY 3
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#define BCM63268_TCLK_DSL 4
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#define BCM63268_TCLK_WO_EPHY 5
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#define BCM63268_TCLK_WO_DSL 6
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#define BCM63268_TCLK_FAP1 11
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#define BCM63268_TCLK_FAP2 15
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#define BCM63268_TCLK_UTO_50 16
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#define BCM63268_TCLK_UTO_EXT 17
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#define BCM63268_TCLK_USB_REF 18
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#define BCM63268_TCLK_SW_RST 29
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#define BCM63268_TCLK_HW_RST 30
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#define BCM63268_TCLK_POR_RST 31
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#endif /* __DT_BINDINGS_CLOCK_BCM63268_H */
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