Bin Meng 7f1a30fdeb riscv: clint: Update the sifive clint ipi driver to support aclint
This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.

The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint ipi driver to
support ACLINT mswi device, by checking the per-driver data field of
the ACLINT mtimer driver to determine whether a syscon based approach
needs to be taken to get the base address of the ACLINT mswi device.

[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
2023-07-12 13:21:40 +08:00
..
2022-09-26 14:29:13 +08:00
2020-05-18 18:36:55 -04:00
2023-02-10 07:41:39 -05:00
2021-04-08 15:37:29 +08:00
2022-09-29 16:11:31 -04:00