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0afdc32d7c
The Parade DP501 is a DP & DVI/HDMI dual-mode transmitter. It enables an RGB/Parallel SOC output to be converted, packed and serialized into either DP or TMDS output device. Only DisplayPort functionality of this transmitter has been implemented and tested. Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
580 lines
12 KiB
C
580 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024 Jonas Schwöbel <jonasschwoebel@yahoo.de>
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* Copyright (C) 2024 Svyatoslav Ryhel <clamor95@gmail.com>
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*/
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#include <dm.h>
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#include <i2c.h>
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#include <log.h>
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#include <backlight.h>
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#include <panel.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <power/regulator.h>
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#include <asm/gpio.h>
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/* TOP */
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#define TOPCFG0 0x00
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#define ROMI2C_PRESCALE 0x01
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#define HDCPI2C_PRESCALE 0x02
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#define GPIO 0x03
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#define GPIO_OUT_ENB 0x04
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#define TESTI2C_CTL 0x05
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#define I2CMTIMEOUT 0x06
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#define TOPCFG1 0x07
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#define TOPCFG2 0x08
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#define TOPCFG3 0x09
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#define TOPCFG4 0x0A
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#define CLKSWRST 0x0B
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#define CADETB_CTL 0x0C
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/* Video Attribute */
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#define HTOTAL_L 0x10
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#define HTOTAL_H 0x11
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#define HSTART_L 0x12
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#define HSTART_H 0x13
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#define HWIDTH_L 0x14
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#define HWIDTH_H 0x15
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#define VTOTAL_L 0x16
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#define VTOTAL_H 0x17
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#define VSTART_L 0x18
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#define VSTART_H 0x19
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#define VHEIGHT_L 0x1A
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#define VHEIGHT_H 0x1B
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#define HSPHSW_L 0x1C
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#define HSPHSW_H 0x1D
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#define VSPVSW_L 0x1E
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#define VSPVSW_H 0x1F
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#define MISC0 0x20
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#define MISC1 0x21
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/* Video Capture */
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#define VCAPCTRL0 0x24
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#define VCAPCTRL1 0x25
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#define VCAPCTRL2 0x26
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#define VCAPCTRL3 0x27
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#define VCAPCTRL4 0x28
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#define VCAP_MEASURE 0x29
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/* Main Link Control */
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#define NVID_L 0x2C
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#define NVID_M 0x2D
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#define NVID_H 0x2E
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#define LINK_CTRL0 0x2F
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#define LINK_CTRL1 0x30
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#define LINK_DEBUG 0x31
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#define ERR_POS 0x32
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#define ERR_PAT 0x33
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#define LINK_DEB_SEL 0x34
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#define IDLE_PATTERN 0x35
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#define TU_SIZE 0x36
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#define CRC_CTRL 0x37
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#define CRC_OUT 0x38
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/* AVI-2 InfoFrame */
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#define SD_CTRL0 0x3A
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#define SD_CTRL1 0x3B
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#define SD_HB0 0x3C
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#define SD_HB1 0x3D
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#define SD_HB2 0x3E
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#define SD_HB3 0x3F
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#define SD_DB0 0x40
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#define SD_DB1 0x41
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#define SD_DB2 0x42
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#define SD_DB3 0x43
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#define SD_DB4 0x44
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#define SD_DB5 0x45
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#define SD_DB6 0x46
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#define SD_DB7 0x47
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#define SD_DB8 0x48
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#define SD_DB9 0x49
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#define SD_DB10 0x4A
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#define SD_DB11 0x4B
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#define SD_DB12 0x4C
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#define SD_DB13 0x4D
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#define SD_DB14 0x4E
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#define SD_DB15 0x4F
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/* Aux Channel and PCS */
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#define DPCD_REV 0X50
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#define MAX_LINK_RATE 0x51
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#define MAX_LANE_COUNT 0x52
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#define MAX_DOWNSPREAD 0x53
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#define NORP 0x54
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#define DOWNSTRMPORT_PRE 0x55
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#define MLINK_CH_CODING 0x56
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#define RCV_P0_CAP0 0x58
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#define RCV_P0_CAP1 0x59
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#define RCV_P1_CAP0 0x5A
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#define RCV_P1_CAP1 0x5B
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#define DOWNSPREAD_CTL 0x5C
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#define LINK_BW 0x5D
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#define LANE_CNT 0x5E
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#define TRAINING_CTL 0x5F
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#define QUALTEST_CTL 0x60
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#define SINK_COUNT 0x61
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#define DEV_SERVICE_IRQ 0x62
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#define LANE01_STATUS 0x63
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#define LANE23_STATUS 0x64
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#define LANE_STATUS_UPDATE 0x65
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#define SINK_STATUS 0x66
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#define AUX_NOISE 0x67
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#define TEST_MODE 0x69
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#define TEST_PATTERN0 0x6A
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#define TEST_PATTERN1 0x6B
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#define TEST_PATTERN2 0x6C
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#define SIGNATURE 0x6D
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#define PCSCFG 0x6E
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#define AUXCTRL0 0x6f
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#define AUXCTRL2 0x70
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#define AUXCTRL1 0x71
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#define HPDCTL0 0x72
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#define HPDCTL1 0x73
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#define LINK_STATE_CTRL 0x74
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#define SWRST 0x75
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#define LINK_IRQ 0x76
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#define AUXIRQ_CTRL 0x77
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#define HPD2_IRQ_CTRL 0x78
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#define SW_TRAIN_CTRL 0x79
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#define SW_DRV_SET 0x7A
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#define SW_PRE_SET 0x7B
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#define DPCD_ADDR_L 0x7D
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#define DPCD_ADDR_M 0x7E
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#define DPCD_ADDR_H 0x7F
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#define DPCD_LENGTH 0x80
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#define DPCD_WDATA 0x81
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#define DPCD_RDATA 0x82
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#define DPCD_CTL 0x83
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#define DPCD_STATUS 0x84
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#define AUX_STATUS 0x85
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#define I2CTOAUX_RELENGTH 0x86
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#define AUX_RETRY_CTRL 0x87
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#define TIMEOUT_CTRL 0x88
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#define I2CCMD_OPT1 0x89
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#define AUXCMD_ERR_IRQ 0x8A
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#define AUXCMD_OPT2 0x8B
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#define HDCP_Reserved 0x8C
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/* Audio InfoFrame */
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#define TX_MVID0 0x90
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#define TX_MVID1 0x91
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#define TX_MVID2 0x92
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#define TX_MVID_OFF 0x93
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#define TX_MAUD0 0x94
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#define TX_MAUD1 0x95
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#define TX_MAUD2 0x96
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#define TX_MAUD_OFF 0x97
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#define MN_CTRL 0x98
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#define MOUT0 0x99
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#define MOUT1 0x9A
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#define MOUT2 0x9B
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/* Audio Control */
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#define NAUD_L 0x9F
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#define NAUD_M 0xA0
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#define NAUD_H 0xA1
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#define AUD_CTRL0 0xA2
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#define AUD_CTRL1 0xA3
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#define LANE_POL 0xAA
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#define LANE_EN 0xAB
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#define LANE_MAP 0xAC
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#define SCR_POLY0 0xAD
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#define SCR_POLY1 0xAE
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#define PRBS7_POLY 0xAF
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/* Video Pre-process */
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#define MISC_SHDOW 0xB0
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#define VCAPCPCTL0 0xB1
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#define VCAPCPCTL1 0xB2
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#define VCAPCPCTL2 0xB3
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#define CSCPAR 0xB4
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#define I2CTODPCDSTATUS2 0xBA
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#define AUXCTL_REG 0xBB
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/* Page 2 */
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#define SEL_PIO1 0x24
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#define SEL_PIO2 0x25
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#define SEL_PIO3 0x26
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#define CHIP_VER_L 0x82
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struct dp501_priv {
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struct udevice *panel;
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struct display_timing timing;
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struct udevice *chip2;
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struct udevice *vdd;
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struct gpio_desc reset_gpio;
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struct gpio_desc enable_gpio;
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};
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static int dp501_sw_init(struct udevice *dev)
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{
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struct dp501_priv *priv = dev_get_priv(dev);
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int i;
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u8 val;
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dm_i2c_reg_write(dev, TOPCFG4, 0x30);
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udelay(200);
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dm_i2c_reg_write(dev, TOPCFG4, 0x0c);
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dm_i2c_reg_write(dev, 0x8f, 0x02);
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/* check for connected panel during 1 msec */
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for (i = 0; i < 5; i++) {
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val = dm_i2c_reg_read(dev, 0x8d);
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val &= BIT(2);
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if (val)
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break;
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udelay(200);
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}
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if (!val) {
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log_debug("%s: panel is not connected!\n", __func__);
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return -ENODEV;
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}
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dm_i2c_reg_write(priv->chip2, SEL_PIO1, 0x02);
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dm_i2c_reg_write(priv->chip2, SEL_PIO2, 0x04);
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dm_i2c_reg_write(priv->chip2, SEL_PIO3, 0x10);
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dm_i2c_reg_write(dev, LINK_STATE_CTRL, 0xa0);
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dm_i2c_reg_write(dev, 0x8f, 0x02);
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dm_i2c_reg_write(dev, TOPCFG1, 0x16);
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dm_i2c_reg_write(dev, TOPCFG0, 0x24);
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dm_i2c_reg_write(dev, HPD2_IRQ_CTRL, 0x30);
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dm_i2c_reg_write(dev, AUXIRQ_CTRL, 0xff);
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dm_i2c_reg_write(dev, LINK_IRQ, 0xff);
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/* auto detect DVO timing */
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dm_i2c_reg_write(dev, VCAPCTRL3, 0x30);
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/* reset tpfifo at v blank */
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dm_i2c_reg_write(dev, LINK_CTRL0, 0x82);
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dm_i2c_reg_write(dev, VCAPCTRL4, 0x07);
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dm_i2c_reg_write(dev, AUX_RETRY_CTRL, 0x7f);
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dm_i2c_reg_write(dev, TIMEOUT_CTRL, 0x1e);
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dm_i2c_reg_write(dev, AUXCTL_REG, 0x06);
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/* DPCD readable */
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dm_i2c_reg_write(dev, HPDCTL0, 0xa9);
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/* Scramble on */
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dm_i2c_reg_write(dev, QUALTEST_CTL, 0x00);
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dm_i2c_reg_write(dev, 0x8f, 0x02);
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dm_i2c_reg_write(dev, VCAPCTRL0, 0xc4);
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/* set color depth 8bit (0x00: 6bit; 0x20: 8bit; 0x40: 10bit) */
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dm_i2c_reg_write(dev, MISC0, 0x20);
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dm_i2c_reg_write(dev, VCAPCPCTL2, 0x01);
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/* check if bridge returns ready status */
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for (i = 0; i < 5; i++) {
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val = dm_i2c_reg_read(dev, LINK_IRQ);
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val &= BIT(0);
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if (val)
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break;
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udelay(200);
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}
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if (!val) {
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log_debug("%s: bridge is not ready\n", __func__);
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return -ENODEV;
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}
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return 0;
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}
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static void dpcd_configure(struct udevice *dev, u32 config, bool write)
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{
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dm_i2c_reg_write(dev, DPCD_ADDR_L, (u8)(config >> 8));
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dm_i2c_reg_write(dev, DPCD_ADDR_M, (u8)(config >> 16));
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dm_i2c_reg_write(dev, DPCD_ADDR_H, (u8)((config >> 24) | BIT(7)));
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dm_i2c_reg_write(dev, DPCD_LENGTH, 0x00);
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dm_i2c_reg_write(dev, LINK_IRQ, 0x20);
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if (write)
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dm_i2c_reg_write(dev, DPCD_WDATA, (u8)(config & 0xff));
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dm_i2c_reg_write(dev, DPCD_CTL, 0x01);
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udelay(10);
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}
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static int dump_dpcd_data(struct udevice *dev, u32 config, u8 *data)
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{
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int i;
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u8 value;
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dpcd_configure(dev, config, false);
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value = dm_i2c_reg_read(dev, DPCD_CTL);
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if (value)
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return -ENODATA;
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for (i = 0; i < 5; i++) {
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value = dm_i2c_reg_read(dev, LINK_IRQ);
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value &= BIT(5);
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if (value)
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break;
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udelay(100);
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}
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if (!value)
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return -ENODATA;
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value = dm_i2c_reg_read(dev, DPCD_STATUS);
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if (!(value & 0xe0))
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*data = dm_i2c_reg_read(dev, DPCD_RDATA);
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else
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return -ENODATA;
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return 0;
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}
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static int dp501_dpcd_dump(struct udevice *dev, u32 config, u8 *data)
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{
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int i, ret;
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for (i = 0; i < 5; i++) {
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ret = dump_dpcd_data(dev, config, data);
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if (!ret)
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break;
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udelay(100);
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}
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return ret;
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}
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static int dp501_reset_link(struct udevice *dev)
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{
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dm_i2c_reg_write(dev, TRAINING_CTL, 0x00);
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dm_i2c_reg_write(dev, SWRST, 0xf8);
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dm_i2c_reg_write(dev, SWRST, 0x00);
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return -ENODEV;
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}
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static int dp501_link_training(struct udevice *dev)
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{
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int i, ret;
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u8 lane, link, link_out;
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u8 lane_cnt, lane01, lane23;
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dpcd_configure(dev, 0x030000, true);
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dpcd_configure(dev, 0x03011c, true);
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dpcd_configure(dev, 0x0301f8, true);
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ret = dp501_dpcd_dump(dev, 0x90000100, &link);
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if (ret) {
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log_debug("%s: link dump failed %d\n", __func__, ret);
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return dp501_reset_link(dev);
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}
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ret = dp501_dpcd_dump(dev, 0x90000200, &lane);
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if (ret) {
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log_debug("%s: lane dump failed %d\n", __func__, ret);
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return dp501_reset_link(dev);
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}
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/* Software trainig */
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for (i = 10; i > 0; i--) {
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dm_i2c_reg_write(dev, LINK_BW, link);
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dm_i2c_reg_write(dev, LANE_CNT, lane | BIT(7));
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link_out = dm_i2c_reg_read(dev, LINK_BW);
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lane_cnt = dm_i2c_reg_read(dev, LANE_CNT);
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if (link_out == link &&
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(lane_cnt == (lane | BIT(7))))
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break;
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udelay(500);
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}
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if (!i)
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return dp501_reset_link(dev);
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dm_i2c_reg_write(dev, LINK_STATE_CTRL, 0x00);
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dm_i2c_reg_write(dev, TRAINING_CTL, 0x0d);
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/* check if bridge returns link ready status */
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for (i = 0; i < 100; i++) {
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link_out = dm_i2c_reg_read(dev, LINK_IRQ);
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link_out &= BIT(1);
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if (link_out) {
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dm_i2c_reg_write(dev, LINK_IRQ, 0xff);
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break;
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}
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udelay(100);
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}
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if (!link_out) {
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log_debug("%s: link prepare failed %d\n",
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__func__, link_out);
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return dp501_reset_link(dev);
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}
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lane01 = dm_i2c_reg_read(dev, LANE01_STATUS);
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lane23 = dm_i2c_reg_read(dev, LANE23_STATUS);
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switch (lane_cnt & 0xf) {
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case 4:
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if (lane01 == 0x77 &&
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lane23 == 0x77)
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return 0;
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break;
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case 2:
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if (lane01 == 0x77)
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return 0;
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break;
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default:
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if ((lane01 & 7) == 7)
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return 0;
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break;
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}
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return dp501_reset_link(dev);
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}
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static int dp501_attach(struct udevice *dev)
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{
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struct dp501_priv *priv = dev_get_priv(dev);
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int ret;
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ret = dp501_sw_init(dev);
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if (ret)
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return ret;
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mdelay(90);
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ret = dp501_link_training(dev);
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if (ret)
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return ret;
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/* Perform panel HW setup */
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return panel_enable_backlight(priv->panel);
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}
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static int dp501_set_backlight(struct udevice *dev, int percent)
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{
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struct dp501_priv *priv = dev_get_priv(dev);
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return panel_set_backlight(priv->panel, percent);
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}
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static int dp501_panel_timings(struct udevice *dev,
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struct display_timing *timing)
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{
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struct dp501_priv *priv = dev_get_priv(dev);
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memcpy(timing, &priv->timing, sizeof(*timing));
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return 0;
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}
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static void dp501_hw_init(struct dp501_priv *priv)
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{
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dm_gpio_set_value(&priv->reset_gpio, 1);
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regulator_set_enable_if_allowed(priv->vdd, 1);
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dm_gpio_set_value(&priv->enable_gpio, 1);
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udelay(100);
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dm_gpio_set_value(&priv->reset_gpio, 0);
|
|
mdelay(80);
|
|
}
|
|
|
|
static int dp501_setup(struct udevice *dev)
|
|
{
|
|
struct dm_i2c_chip *chip = dev_get_parent_plat(dev);
|
|
struct dp501_priv *priv = dev_get_priv(dev);
|
|
struct udevice *bus = dev_get_parent(dev);
|
|
int ret;
|
|
|
|
/* get panel */
|
|
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev,
|
|
"panel", &priv->panel);
|
|
if (ret) {
|
|
log_debug("%s: Cannot get panel: ret=%d\n", __func__, ret);
|
|
return log_ret(ret);
|
|
}
|
|
|
|
/* get regulators */
|
|
ret = device_get_supply_regulator(dev, "power-supply", &priv->vdd);
|
|
if (ret) {
|
|
log_debug("%s: vddc regulator error: %d\n", __func__, ret);
|
|
if (ret != -ENOENT)
|
|
return log_ret(ret);
|
|
}
|
|
|
|
/* get gpios */
|
|
ret = gpio_request_by_name(dev, "reset-gpios", 0,
|
|
&priv->reset_gpio, GPIOD_IS_OUT);
|
|
if (ret) {
|
|
log_debug("%s: Could not decode reset-gpios (%d)\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = gpio_request_by_name(dev, "enable-gpios", 0,
|
|
&priv->enable_gpio, GPIOD_IS_OUT);
|
|
if (ret) {
|
|
log_debug("%s: Could not decode enable-gpios (%d)\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = i2c_get_chip(bus, chip->chip_addr + 2, 1, &priv->chip2);
|
|
if (ret) {
|
|
log_debug("%s: cannot get second PMIC I2C chip (err %d)\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
dp501_hw_init(priv);
|
|
|
|
/* get EDID */
|
|
return panel_get_display_timing(priv->panel, &priv->timing);
|
|
}
|
|
|
|
static int dp501_probe(struct udevice *dev)
|
|
{
|
|
if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
|
|
return -EPROTONOSUPPORT;
|
|
|
|
return dp501_setup(dev);
|
|
}
|
|
|
|
struct panel_ops dp501_ops = {
|
|
.enable_backlight = dp501_attach,
|
|
.set_backlight = dp501_set_backlight,
|
|
.get_display_timing = dp501_panel_timings,
|
|
};
|
|
|
|
static const struct udevice_id dp501_ids[] = {
|
|
{ .compatible = "parade,dp501" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(dp501) = {
|
|
.name = "dp501",
|
|
.id = UCLASS_PANEL,
|
|
.of_match = dp501_ids,
|
|
.ops = &dp501_ops,
|
|
.probe = dp501_probe,
|
|
.priv_auto = sizeof(struct dp501_priv),
|
|
};
|