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Add firmware interface related headers and macros for ICSSG Ethernet driver. These macros will be later used by the ICSSG ethernet driver. Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com> Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
210 lines
7.5 KiB
C
210 lines
7.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Texas Instruments ICSSG Ethernet driver
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*
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* Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
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*
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*/
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#ifndef __NET_TI_ICSSG_SWITCH_MAP_H
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#define __NET_TI_ICSSG_SWITCH_MAP_H
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/*Time after which FDB entries are checked for aged out values. Value in nanoseconds*/
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#define FDB_AGEING_TIMEOUT_OFFSET 0x0014
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/*default VLAN tag for Host Port*/
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#define HOST_PORT_DF_VLAN_OFFSET 0x001C
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/*Same as HOST_PORT_DF_VLAN_OFFSET*/
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#define EMAC_ICSSG_SWITCH_PORT0_DEFAULT_VLAN_OFFSET HOST_PORT_DF_VLAN_OFFSET
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/*default VLAN tag for P1 Port*/
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#define P1_PORT_DF_VLAN_OFFSET 0x0020
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/*Same as P1_PORT_DF_VLAN_OFFSET*/
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#define EMAC_ICSSG_SWITCH_PORT1_DEFAULT_VLAN_OFFSET P1_PORT_DF_VLAN_OFFSET
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/*default VLAN tag for P2 Port*/
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#define P2_PORT_DF_VLAN_OFFSET 0x0024
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/*Same as P2_PORT_DF_VLAN_OFFSET*/
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#define EMAC_ICSSG_SWITCH_PORT2_DEFAULT_VLAN_OFFSET P2_PORT_DF_VLAN_OFFSET
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/*VLAN-FID Table offset. 4096 VIDs. 2B per VID = 8KB = 0x2000*/
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#define VLAN_STATIC_REG_TABLE_OFFSET 0x0100
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/*VLAN-FID Table offset for EMAC*/
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#define EMAC_ICSSG_SWITCH_DEFAULT_VLAN_TABLE_OFFSET VLAN_STATIC_REG_TABLE_OFFSET
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/*packet descriptor Q reserved memory*/
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#define PORT_DESC0_HI 0x2104
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/*packet descriptor Q reserved memory*/
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#define PORT_DESC0_LO 0x2F6C
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/*packet descriptor Q reserved memory*/
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#define PORT_DESC1_HI 0x3DD4
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/*packet descriptor Q reserved memory*/
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#define PORT_DESC1_LO 0x4C3C
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/*packet descriptor Q reserved memory*/
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#define HOST_DESC0_HI 0x5AA4
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/*packet descriptor Q reserved memory*/
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#define HOST_DESC0_LO 0x5F0C
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/*packet descriptor Q reserved memory*/
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#define HOST_DESC1_HI 0x6374
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/*packet descriptor Q reserved memory*/
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#define HOST_DESC1_LO 0x67DC
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/*special packet descriptor Q reserved memory*/
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#define HOST_SPPD0 0x7AAC
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/*special packet descriptor Q reserved memory*/
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#define HOST_SPPD1 0x7EAC
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/*_Small_Description_*/
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#define TIMESYNC_FW_WC_CYCLECOUNT_OFFSET 0x83EC
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/*IEP count hi roll over count*/
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#define TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET 0x83F4
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/*_Small_Description_*/
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#define TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET 0x83F8
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/*Set clock descriptor*/
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#define TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET 0x83FC
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/*_Small_Description_*/
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#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET 0x843C
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/*_Small_Description_*/
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#define TIMESYNC_FW_WC_SYNCOUT_REDUCTION_COUNT_OFFSET 0x8440
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/*_Small_Description_*/
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#define TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET 0x8444
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/*Control variable to generate SYNC1*/
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#define TIMESYNC_FW_WC_ISOM_PIN_SIGNAL_EN_OFFSET 0x844C
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/*SystemTime Sync0 periodicity*/
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#define TIMESYNC_FW_ST_SYNCOUT_PERIOD_OFFSET 0x8450
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/*pktTxDelay for P1 = link speed dependent p1 mac delay + p1 phy delay*/
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#define TIMESYNC_FW_WC_PKTTXDELAY_P1_OFFSET 0x8454
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/*pktTxDelay for P2 = link speed dependent p2 mac delay + p2 phy delay*/
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#define TIMESYNC_FW_WC_PKTTXDELAY_P2_OFFSET 0x8458
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/*Set clock operation done signal for next task*/
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#define TIMESYNC_FW_SIG_PNFW_OFFSET 0x845C
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/*Set clock operation done signal for next task*/
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#define TIMESYNC_FW_SIG_TIMESYNCFW_OFFSET 0x8460
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/*New list is copied at this time*/
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#define TAS_CONFIG_CHANGE_TIME 0x000C
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/*config change error counter*/
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#define TAS_CONFIG_CHANGE_ERROR_COUNTER 0x0014
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/*TAS List update pending flag*/
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#define TAS_CONFIG_PENDING 0x0018
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/*TAS list update trigger flag*/
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#define TAS_CONFIG_CHANGE 0x0019
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/*List length for new TAS schedule*/
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#define TAS_ADMIN_LIST_LENGTH 0x001A
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/*Currently active TAS list index*/
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#define TAS_ACTIVE_LIST_INDEX 0x001B
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/*Cycle time for the new TAS schedule*/
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#define TAS_ADMIN_CYCLE_TIME 0x001C
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/*Cycle counts remaining till the TAS list update*/
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#define TAS_CONFIG_CHANGE_CYCLE_COUNT 0x0020
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/*Base Flow ID for sending packets to Host for Slice0*/
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#define PSI_L_REGULAR_FLOW_ID_BASE_OFFSET 0x0024
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/*Same as PSI_L_REGULAR_FLOW_ID_BASE_OFFSET*/
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#define EMAC_ICSSG_SWITCH_PSI_L_REGULAR_FLOW_ID_BASE_OFFSET PSI_L_REGULAR_FLOW_ID_BASE_OFFSET
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/*Base Flow ID for sending mgmt and Tx TS to Host for Slice0*/
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#define PSI_L_MGMT_FLOW_ID_OFFSET 0x0026
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/*Same as PSI_L_MGMT_FLOW_ID_OFFSET*/
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#define EMAC_ICSSG_SWITCH_PSI_L_MGMT_FLOW_ID_BASE_OFFSET PSI_L_MGMT_FLOW_ID_OFFSET
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/*Queue number for Special packets written here*/
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#define SPL_PKT_DEFAULT_PRIORITY 0x0028
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/*Express Preemptible Queue Mask*/
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#define EXPRESS_PRE_EMPTIVE_Q_MASK 0x0029
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/*Port1/Port2 Default Queue number for untagged packets, only 1B is used*/
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#define QUEUE_NUM_UNTAGGED 0x002A
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/*Stores the table used for priority regeneration. 1B per PCP/Queue*/
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#define PORT_Q_PRIORITY_REGEN_OFFSET 0x002C
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/* For marking Packet as priority/express (this feature is disabled) or
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* cut-through/S&F.
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*/
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#define EXPRESS_PRE_EMPTIVE_Q_MAP 0x0034
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/*Stores the table used for priority mapping. 1B per PCP/Queue*/
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#define PORT_Q_PRIORITY_MAPPING_OFFSET 0x003C
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/*TAS gate mask for windows list0*/
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#define TAS_GATE_MASK_LIST0 0x0100
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/*TAS gate mask for windows list1*/
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#define TAS_GATE_MASK_LIST1 0x0350
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/*Memory to Enable/Disable Preemption on TX side*/
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#define PRE_EMPTION_ENABLE_TX 0x05A0
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/*Active State of Preemption on TX side*/
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#define PRE_EMPTION_ACTIVE_TX 0x05A1
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/*Memory to Enable/Disable Verify State Machine Preemption*/
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#define PRE_EMPTION_ENABLE_VERIFY 0x05A2
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/*Verify Status of State Machine*/
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#define PRE_EMPTION_VERIFY_STATUS 0x05A3
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/*Non Final Fragment Size supported by Link Partner*/
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#define PRE_EMPTION_ADD_FRAG_SIZE_REMOTE 0x05A4
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/*Non Final Fragment Size supported by Firmware*/
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#define PRE_EMPTION_ADD_FRAG_SIZE_LOCAL 0x05A6
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/*Time in ms the State machine waits for respond packet*/
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#define PRE_EMPTION_VERIFY_TIME 0x05A8
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/*Memory used for R30 related management commands*/
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#define MGR_R30_CMD_OFFSET 0x05AC
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/*HW Buffer Pool0 base address*/
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#define BUFFER_POOL_0_ADDR_OFFSET 0x05BC
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/*16B for Host Egress MSMC Q (Pre-emptible) context*/
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#define HOST_RX_Q_PRE_CONTEXT_OFFSET 0x0684
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/*Buffer for 8 FDB entries to be added by 'Add Multiple FDB entries IOCTL*/
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#define FDB_CMD_BUFFER 0x0894
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/*16B for Host Egress MSMC Q (Express) context*/
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#define HOST_RX_Q_EXP_CONTEXT_OFFSET 0x0940
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/*Start of 32 bits PA_STAT counters*/
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#define PA_STAT_32b_START_OFFSET 0x0080
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#endif
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/* __NET_TI_ICSSG_SWITCH_MAP_H */
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