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1c05cb469f
Add icssg_config.h / .c and icssg_classifier.c files. These are firmware configuration and classification related files. Add MII helper APIs and MACROs. These APIs and MACROs will be later used by ICSSG Ethernet driver. Also introduce icssg_prueth.h which has definition of prueth related structures. Signed-off-by: MD Danish Anwar <danishanwar@ti.com> Reviewed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
193 lines
6.4 KiB
C
193 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* PRU-ICSS MII_RT register definitions
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*
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* Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com
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*/
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#ifndef __NET_PRUSS_MII_RT_H__
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#define __NET_PRUSS_MII_RT_H__
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#include <regmap.h>
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/* PRUSS_MII_RT Registers */
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#define PRUSS_MII_RT_RXCFG0 0x0
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#define PRUSS_MII_RT_RXCFG1 0x4
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#define PRUSS_MII_RT_TXCFG0 0x10
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#define PRUSS_MII_RT_TXCFG1 0x14
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#define PRUSS_MII_RT_TX_CRC0 0x20
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#define PRUSS_MII_RT_TX_CRC1 0x24
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#define PRUSS_MII_RT_TX_IPG0 0x30
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#define PRUSS_MII_RT_TX_IPG1 0x34
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#define PRUSS_MII_RT_PRS0 0x38
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#define PRUSS_MII_RT_PRS1 0x3c
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#define PRUSS_MII_RT_RX_FRMS0 0x40
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#define PRUSS_MII_RT_RX_FRMS1 0x44
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#define PRUSS_MII_RT_RX_PCNT0 0x48
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#define PRUSS_MII_RT_RX_PCNT1 0x4c
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#define PRUSS_MII_RT_RX_ERR0 0x50
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#define PRUSS_MII_RT_RX_ERR1 0x54
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/* PRUSS_MII_RT_RXCFG0/1 bits */
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#define PRUSS_MII_RT_RXCFG_RX_ENABLE BIT(0)
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#define PRUSS_MII_RT_RXCFG_RX_DATA_RDY_MODE_DIS BIT(1)
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#define PRUSS_MII_RT_RXCFG_RX_CUT_PREAMBLE BIT(2)
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#define PRUSS_MII_RT_RXCFG_RX_MUX_SEL BIT(3)
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#define PRUSS_MII_RT_RXCFG_RX_L2_EN BIT(4)
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#define PRUSS_MII_RT_RXCFG_RX_BYTE_SWAP BIT(5)
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#define PRUSS_MII_RT_RXCFG_RX_AUTO_FWD_PRE BIT(6)
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#define PRUSS_MII_RT_RXCFG_RX_L2_EOF_SCLR_DIS BIT(9)
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/* PRUSS_MII_RT_TXCFG0/1 bits */
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#define PRUSS_MII_RT_TXCFG_TX_ENABLE BIT(0)
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#define PRUSS_MII_RT_TXCFG_TX_AUTO_PREAMBLE BIT(1)
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#define PRUSS_MII_RT_TXCFG_TX_EN_MODE BIT(2)
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#define PRUSS_MII_RT_TXCFG_TX_BYTE_SWAP BIT(3)
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#define PRUSS_MII_RT_TXCFG_TX_MUX_SEL BIT(8)
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#define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_SEQUENCE BIT(9)
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#define PRUSS_MII_RT_TXCFG_PRE_TX_AUTO_ESC_ERR BIT(10)
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#define PRUSS_MII_RT_TXCFG_TX_32_MODE_EN BIT(11)
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#define PRUSS_MII_RT_TXCFG_TX_IPG_WIRE_CLK_EN BIT(12) /* SR2.0 onwards */
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#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_SHIFT 16
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#define PRUSS_MII_RT_TXCFG_TX_START_DELAY_MASK GENMASK(25, 16)
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#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_SHIFT 28
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#define PRUSS_MII_RT_TXCFG_TX_CLK_DELAY_MASK GENMASK(30, 28)
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/* PRUSS_MII_RT_TX_IPG0/1 bits */
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#define PRUSS_MII_RT_TX_IPG_IPG_SHIFT 0
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#define PRUSS_MII_RT_TX_IPG_IPG_MASK GENMASK(9, 0)
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/* PRUSS_MII_RT_PRS0/1 bits */
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#define PRUSS_MII_RT_PRS_COL BIT(0)
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#define PRUSS_MII_RT_PRS_CRS BIT(1)
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/* PRUSS_MII_RT_RX_FRMS0/1 bits */
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#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_SHIFT 0
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#define PRUSS_MII_RT_RX_FRMS_MIN_FRM_MASK GENMASK(15, 0)
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#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_SHIFT 16
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#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_MASK GENMASK(31, 16)
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/* Min/Max in MII_RT_RX_FRMS */
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/* For EMAC and Switch */
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#define PRUSS_MII_RT_RX_FRMS_MAX (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
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#define PRUSS_MII_RT_RX_FRMS_MIN_FRM (64)
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/* for HSR and PRP */
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#define PRUSS_MII_RT_RX_FRMS_MAX_FRM_LRE (PRUSS_MII_RT_RX_FRMS_MAX + \
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ICSS_LRE_TAG_RCT_SIZE)
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/* PRUSS_MII_RT_RX_PCNT0/1 bits */
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#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_SHIFT 0
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#define PRUSS_MII_RT_RX_PCNT_MIN_PCNT_MASK GENMASK(3, 0)
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#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_SHIFT 4
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#define PRUSS_MII_RT_RX_PCNT_MAX_PCNT_MASK GENMASK(7, 4)
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/* PRUSS_MII_RT_RX_ERR0/1 bits */
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#define PRUSS_MII_RT_RX_ERR_MIN_PCNT_ERR BIT(0)
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#define PRUSS_MII_RT_RX_ERR_MAX_PCNT_ERR BIT(1)
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#define PRUSS_MII_RT_RX_ERR_MIN_FRM_ERR BIT(2)
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#define PRUSS_MII_RT_RX_ERR_MAX_FRM_ERR BIT(3)
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#define ICSSG_CFG_OFFSET 0
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#define RGMII_CFG_OFFSET 4
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/* Constant to choose between MII0 and MII1 */
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#define ICSS_MII0 0
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#define ICSS_MII1 1
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/* ICSSG_CFG Register bits */
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#define ICSSG_CFG_SGMII_MODE BIT(16)
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#define ICSSG_CFG_TX_PRU_EN BIT(11)
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#define ICSSG_CFG_RX_SFD_TX_SOF_EN BIT(10)
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#define ICSSG_CFG_RTU_PRU_PSI_SHARE_EN BIT(9)
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#define ICSSG_CFG_IEP1_TX_EN BIT(8)
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#define ICSSG_CFG_MII1_MODE GENMASK(6, 5)
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#define ICSSG_CFG_MII1_MODE_SHIFT 5
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#define ICSSG_CFG_MII0_MODE GENMASK(4, 3)
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#define ICSSG_CFG_MII0_MODE_SHIFT 3
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#define ICSSG_CFG_RX_L2_G_EN BIT(2)
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#define ICSSG_CFG_TX_L2_EN BIT(1)
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#define ICSSG_CFG_TX_L1_EN BIT(0)
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enum mii_mode { MII_MODE_MII = 0, MII_MODE_RGMII, MII_MODE_SGMII };
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/* RGMII CFG Register bits */
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#define RGMII_CFG_INBAND_EN_MII0 BIT(16)
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#define RGMII_CFG_GIG_EN_MII0 BIT(17)
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#define RGMII_CFG_INBAND_EN_MII1 BIT(20)
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#define RGMII_CFG_GIG_EN_MII1 BIT(21)
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#define RGMII_CFG_FULL_DUPLEX_MII0 BIT(18)
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#define RGMII_CFG_FULL_DUPLEX_MII1 BIT(22)
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#define RGMII_CFG_SPEED_MII0 GENMASK(2, 1)
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#define RGMII_CFG_SPEED_MII1 GENMASK(6, 5)
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#define RGMII_CFG_SPEED_MII0_SHIFT 1
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#define RGMII_CFG_SPEED_MII1_SHIFT 5
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#define RGMII_CFG_FULLDUPLEX_MII0 BIT(3)
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#define RGMII_CFG_FULLDUPLEX_MII1 BIT(7)
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#define RGMII_CFG_FULLDUPLEX_MII0_SHIFT 3
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#define RGMII_CFG_FULLDUPLEX_MII1_SHIFT 7
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#define RGMII_CFG_SPEED_10M 0
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#define RGMII_CFG_SPEED_100M 1
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#define RGMII_CFG_SPEED_1G 2
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static inline void icssg_mii_update_ipg(struct regmap *mii_rt, int mii, u32 ipg)
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{
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u32 val;
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if (mii == ICSS_MII0) {
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regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, ipg);
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} else {
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/* Errata workaround: IEP1 is not read by h/w unless IEP0 is written */
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regmap_read(mii_rt, PRUSS_MII_RT_TX_IPG0, &val);
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regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG1, ipg);
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regmap_write(mii_rt, PRUSS_MII_RT_TX_IPG0, val);
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}
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}
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static inline void icssg_update_rgmii_cfg(struct regmap *miig_rt, int speed,
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bool full_duplex, int slice, struct prueth_priv *priv)
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{
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u32 gig_en_mask, gig_val = 0, full_duplex_mask, full_duplex_val = 0;
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u32 inband_en_mask, inband_val = 0;
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gig_en_mask = (slice == ICSS_MII0) ? RGMII_CFG_GIG_EN_MII0 :
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RGMII_CFG_GIG_EN_MII1;
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if (speed == SPEED_1000)
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gig_val = gig_en_mask;
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regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, gig_en_mask, gig_val);
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inband_en_mask = (slice == ICSS_MII0) ? RGMII_CFG_INBAND_EN_MII0 :
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RGMII_CFG_INBAND_EN_MII1;
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if (speed == SPEED_10 && phy_interface_is_rgmii(priv->phydev))
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inband_val = inband_en_mask;
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regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, inband_en_mask, inband_val);
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full_duplex_mask = (slice == ICSS_MII0) ? RGMII_CFG_FULL_DUPLEX_MII0 :
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RGMII_CFG_FULL_DUPLEX_MII1;
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if (full_duplex)
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full_duplex_val = full_duplex_mask;
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regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, full_duplex_mask,
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full_duplex_val);
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}
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static inline void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, int phy_if)
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{
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u32 val, mask, shift;
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mask = mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE : ICSSG_CFG_MII1_MODE;
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shift = mii == ICSS_MII0 ? ICSSG_CFG_MII0_MODE_SHIFT : ICSSG_CFG_MII1_MODE_SHIFT;
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val = MII_MODE_RGMII;
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if (phy_if == PHY_INTERFACE_MODE_MII)
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val = MII_MODE_MII;
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val <<= shift;
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regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, mask, val);
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regmap_read(miig_rt, ICSSG_CFG_OFFSET, &val);
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}
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#endif /* __NET_PRUSS_MII_RT_H__ */
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