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99e791746f
clk_set_rate() should return the clock rate that was set. The IPQ4019 clock driver doesn't set any rates yet but it should still return the expected value so that drivers can work properly. For a baud rate of 115200 with an expected bit clock divisor of 16, the clock rate should be 1843200 so return that frequency. Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
148 lines
4.3 KiB
C
148 lines
4.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Clock drivers for Qualcomm IPQ40xx
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*
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* Copyright (c) 2020 Sartura Ltd.
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*
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* Author: Robert Marko <robert.marko@sartura.hr>
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*
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*/
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#include <clk-uclass.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
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#include "clock-qcom.h"
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static ulong ipq4019_clk_set_rate(struct clk *clk, ulong rate)
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{
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switch (clk->id) {
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case GCC_BLSP1_UART1_APPS_CLK: /*UART1*/
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/* This clock is already initialized by SBL1 */
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return 1843200;
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default:
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return -EINVAL;
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}
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}
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static int ipq4019_clk_enable(struct clk *clk)
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{
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switch (clk->id) {
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case GCC_BLSP1_QUP1_SPI_APPS_CLK: /*SPI1*/
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/* This clock is already initialized by SBL1 */
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return 0;
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case GCC_PRNG_AHB_CLK: /*PRNG*/
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/* This clock is already initialized by SBL1 */
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return 0;
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case GCC_USB3_MASTER_CLK:
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case GCC_USB3_SLEEP_CLK:
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case GCC_USB3_MOCK_UTMI_CLK:
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case GCC_USB2_MASTER_CLK:
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case GCC_USB2_SLEEP_CLK:
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case GCC_USB2_MOCK_UTMI_CLK:
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/* These clocks is already initialized by SBL1 */
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return 0;
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default:
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return -EINVAL;
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}
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}
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static const struct qcom_reset_map gcc_ipq4019_resets[] = {
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[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
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[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
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[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
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[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
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[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
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[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
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[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
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[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
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[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
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[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
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[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
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[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
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[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
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[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
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[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
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[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
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[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
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[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
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[PCIE_AHB_ARES] = { 0x1d010, 10 },
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[PCIE_PWR_ARES] = { 0x1d010, 9 },
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[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
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[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
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[PCIE_PHY_ARES] = { 0x1d010, 6 },
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[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
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[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
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[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
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[PCIE_PIPE_ARES] = { 0x1d010, 2 },
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[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
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[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
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[ESS_RESET] = { 0x12008, 0},
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[GCC_BLSP1_BCR] = {0x01000, 0},
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[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
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[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
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[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
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[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
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[GCC_BIMC_BCR] = {0x04000, 0},
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[GCC_TLMM_BCR] = {0x05000, 0},
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[GCC_IMEM_BCR] = {0x0E000, 0},
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[GCC_ESS_BCR] = {0x12008, 0},
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[GCC_PRNG_BCR] = {0x13000, 0},
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[GCC_BOOT_ROM_BCR] = {0x13008, 0},
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[GCC_CRYPTO_BCR] = {0x16000, 0},
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[GCC_SDCC1_BCR] = {0x18000, 0},
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[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
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[GCC_AUDIO_BCR] = {0x1B008, 0},
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[GCC_QPIC_BCR] = {0x1C000, 0},
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[GCC_PCIE_BCR] = {0x1D000, 0},
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[GCC_USB2_BCR] = {0x1E008, 0},
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[GCC_USB2_PHY_BCR] = {0x1E018, 0},
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[GCC_USB3_BCR] = {0x1E024, 0},
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[GCC_USB3_PHY_BCR] = {0x1E034, 0},
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[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
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[GCC_PCNOC_BCR] = {0x2102C, 0},
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[GCC_DCD_BCR] = {0x21038, 0},
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[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
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[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
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[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
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[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
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[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
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[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
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[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
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[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
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[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
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[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
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[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
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[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
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[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
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[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
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[GCC_TCSR_BCR] = {0x22000, 0},
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[GCC_MPM_BCR] = {0x24000, 0},
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[GCC_SPDM_BCR] = {0x25000, 0},
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};
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static struct msm_clk_data ipq4019_clk_data = {
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.enable = ipq4019_clk_enable,
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.set_rate = ipq4019_clk_set_rate,
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.resets = gcc_ipq4019_resets,
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.num_resets = ARRAY_SIZE(gcc_ipq4019_resets),
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};
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static const struct udevice_id gcc_ipq4019_of_match[] = {
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{
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.compatible = "qcom,gcc-ipq4019",
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.data = (ulong)&ipq4019_clk_data,
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},
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{ }
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};
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U_BOOT_DRIVER(gcc_ipq4019) = {
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.name = "gcc_ipq4019",
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.id = UCLASS_NOP,
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.of_match = gcc_ipq4019_of_match,
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.bind = qcom_cc_bind,
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.flags = DM_FLAG_PRE_RELOC,
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};
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