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6e992a6bc8
SE HMIBSC board uses UART1 as the main debug console, so add corresponding clocks and pinmux support. Along with that update instructions to enable clocks for debug UART support. Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
144 lines
3.4 KiB
C
144 lines
3.4 KiB
C
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* Clock drivers for Qualcomm APQ8016
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*
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* (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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*
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* Based on Little Kernel driver, simplified
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/qcom,gcc-msm8916.h>
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#include "clock-qcom.h"
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/* Clocks: (from CLK_CTL_BASE) */
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#define GPLL0_STATUS (0x2101C)
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#define APCS_GPLL_ENA_VOTE (0x45000)
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#define APCS_CLOCK_BRANCH_ENA_VOTE (0x45004)
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#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
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#define SDCC_CMD_RCGR(n) (((n + 1) * 0x1000) + 0x41004)
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#define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018)
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#define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C)
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/* BLSP1 AHB clock (root clock for BLSP) */
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#define BLSP1_AHB_CBCR 0x1008
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/* Uart clock control registers */
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#define BLSP1_UART1_APPS_CBCR (0x203C)
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#define BLSP1_UART1_APPS_CMD_RCGR (0x2044)
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#define BLSP1_UART2_APPS_CBCR (0x302C)
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#define BLSP1_UART2_APPS_CMD_RCGR (0x3034)
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/* GPLL0 clock control registers */
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#define GPLL0_STATUS_ACTIVE BIT(17)
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static struct pll_vote_clk gpll0_vote_clk = {
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.status = GPLL0_STATUS,
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.status_bit = GPLL0_STATUS_ACTIVE,
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.ena_vote = APCS_GPLL_ENA_VOTE,
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.vote_bit = BIT(0),
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};
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static struct vote_clk gcc_blsp1_ahb_clk = {
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.cbcr_reg = BLSP1_AHB_CBCR,
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.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
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.vote_bit = BIT(10),
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};
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/* SDHCI */
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static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate)
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{
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int div = 15; /* 100MHz default */
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if (rate == 200000000)
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div = 4;
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clk_enable_cbc(priv->base + SDCC_AHB_CBCR(slot));
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/* 800Mhz/div, gpll0 */
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clk_rcg_set_rate_mnd(priv->base, SDCC_CMD_RCGR(slot), div, 0, 0,
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CFG_CLK_SRC_GPLL0, 8);
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clk_enable_gpll0(priv->base, &gpll0_vote_clk);
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clk_enable_cbc(priv->base + SDCC_APPS_CBCR(slot));
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return rate;
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}
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/* UART: 115200 */
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int apq8016_clk_init_uart(phys_addr_t base, unsigned long id)
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{
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u32 cmd_rcgr, apps_cbcr;
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switch (id) {
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case GCC_BLSP1_UART1_APPS_CLK:
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cmd_rcgr = BLSP1_UART1_APPS_CMD_RCGR;
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apps_cbcr = BLSP1_UART1_APPS_CBCR;
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break;
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case GCC_BLSP1_UART2_APPS_CLK:
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cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR;
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apps_cbcr = BLSP1_UART2_APPS_CBCR;
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break;
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default:
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return 0;
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}
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/* Enable AHB clock */
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clk_enable_vote_clk(base, &gcc_blsp1_ahb_clk);
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/* 7372800 uart block clock @ GPLL0 */
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clk_rcg_set_rate_mnd(base, cmd_rcgr, 1, 144, 15625, CFG_CLK_SRC_GPLL0,
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16);
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/* Vote for gpll0 clock */
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clk_enable_gpll0(base, &gpll0_vote_clk);
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/* Enable core clk */
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clk_enable_cbc(base + apps_cbcr);
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return 0;
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}
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static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case GCC_SDCC1_APPS_CLK: /* SDC1 */
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return apq8016_clk_init_sdc(priv, 0, rate);
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case GCC_SDCC2_APPS_CLK: /* SDC2 */
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return apq8016_clk_init_sdc(priv, 1, rate);
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case GCC_BLSP1_UART1_APPS_CLK: /* UART1 */
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case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */
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apq8016_clk_init_uart(priv->base, clk->id);
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return 7372800;
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default:
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return 0;
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}
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}
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static struct msm_clk_data apq8016_clk_data = {
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.set_rate = apq8016_clk_set_rate,
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};
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static const struct udevice_id gcc_apq8016_of_match[] = {
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{
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.compatible = "qcom,gcc-msm8916",
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.data = (ulong)&apq8016_clk_data,
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},
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{ }
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};
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U_BOOT_DRIVER(gcc_apq8016) = {
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.name = "gcc_apq8016",
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.id = UCLASS_NOP,
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.of_match = gcc_apq8016_of_match,
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.bind = qcom_cc_bind,
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.flags = DM_FLAG_PRE_RELOC,
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};
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