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313ffe2746
Unlike CMPC885 and CMPCPRO boards, the FPGA of MCR3000 board doesn't load code automatically but needs to be loaded by software through SPI. Until now it was loaded later by Linux, but we'd like U-boot to have access to some information that require the FPGA, like board address in racks. So, implemented the load of FPGA in U-boot. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> --- To avoid spamming your email boxes, the code isn't included in the emailed patch but will be present in the PULL request
84 lines
1.6 KiB
Plaintext
84 lines
1.6 KiB
Plaintext
/*
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* MCR3000 Device Tree Source
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*
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* Copyright 2017 CS Systemes d'Information
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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soc: immr@ff000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device-type = "soc";
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compatible = "simple-bus";
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ranges = <0 0xff000000 0x4000>;
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reg = <0xff000000 0x00000200>;
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WDT: watchdog@0 {
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compatible = "fsl,pq1-wdt";
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reg = <0x0 0x10>;
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timeout-sec = <2>;
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hw_margin_ms = <1000>;
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};
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spi: spi@aa0 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl,mpc8xx-spi";
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gpios = <&csspi 2 0
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&csspi 0 0>;
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temp@0 {
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reg = <0>;
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compatible = "ti,lm74";
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};
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fpga@1 {
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reg = <1>;
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};
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};
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};
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localbus@ff000100 {
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compatible = "s3k,mcr3000-localbus", "fsl,pq1-localbus", "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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reg = <0xff000100 0x40>; // ORx and BRx register
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ranges = <0 0 0x04000000 0x04000000 // BOOT
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1 0 0x00000000 0x04000000 // SDRAM
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2 0 0x08000000 0x04000000 // RAMDP
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3 0 0x0C000000 0x04000000 // NAND
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4 0 0x10000000 0x04000000 // Periphs
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5 0 0x14000000 0x04000000 // FPGA
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6 0 0x18000000 0x04000000 // mezzanine
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7 0 0x1c000000 0x04000000>; // DSP
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csspi: gpio-controller@2 {
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#gpio-cells = <2>;
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compatible = "s3k,mcr3000-cpld-csspi";
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reg = <4 0x802 2>;
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gpio-controller;
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};
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};
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SERIAL: smc@0 {
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compatible = "fsl,pq1-smc";
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};
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FEC: fec@0 {
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compatible = "fsl,pq1-fec1";
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};
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chosen {
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stdout-path = &SERIAL;
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};
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};
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