mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-08-08 08:16:59 +02:00
c6a13f3d6f
Arm's GIC-600 features a Power Register (GICR_PWRR), which needs to be programmed to enable redistributor operation. Power on the redistributor and wait until the power on state is reflected by checking the bit GICR_PWRR.RDPD == 0. While running U-Boot in EL3 without enabling this register, GICR_WAKER.ChildrenAsleep bit is not getting cleared and loops infinitely. This register(GICR_PWRR) must be programmed to mark the frame as powered on, before accessing other registers in the frame. Rest of initialization sequence remains the same. ARM GIC-600 IP complies with ARM GICv3 architecture. Enable this config if GIC-600 IP present. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
51 lines
898 B
Plaintext
51 lines
898 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
|
|
|
|
if ARCH_VERSAL_NET
|
|
|
|
config SYS_BOARD
|
|
string "Board name"
|
|
default "versal-net"
|
|
|
|
config SYS_VENDOR
|
|
string "Vendor name"
|
|
default "xilinx"
|
|
|
|
config SYS_SOC
|
|
default "versal-net"
|
|
|
|
config COUNTER_FREQUENCY
|
|
int "Timer clock frequency"
|
|
default 0
|
|
help
|
|
Setup time clock frequency for certain platform
|
|
|
|
config IOU_SWITCH_DIVISOR0
|
|
hex "IOU switch divisor0"
|
|
default 0x20
|
|
help
|
|
Setup time clock divisor for input clock.
|
|
|
|
config SYS_MEM_RSVD_FOR_MMU
|
|
bool "Reserve memory for MMU Table"
|
|
help
|
|
If defined this option is used to setup different space for
|
|
MMU table than the one which will be allocated during
|
|
relocation.
|
|
|
|
config GICV3
|
|
def_bool y
|
|
|
|
config GICV3_SUPPORT_GIC600
|
|
def_bool y
|
|
|
|
config SYS_MALLOC_LEN
|
|
default 0x2000000
|
|
|
|
config ZYNQ_SDHCI_MAX_FREQ
|
|
default 200000000
|
|
|
|
source "board/xilinx/Kconfig"
|
|
source "board/xilinx/versal-net/Kconfig"
|
|
|
|
endif
|