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127 lines
3.6 KiB
C
127 lines
3.6 KiB
C
/*
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* Register definitions for Static Memory Controller
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*/
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#ifndef __CPU_AT32AP_HSMC3_H__
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#define __CPU_AT32AP_HSMC3_H__
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/* HSMC3 register offsets */
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#define HSMC3_SETUP0 0x0000
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#define HSMC3_PULSE0 0x0004
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#define HSMC3_CYCLE0 0x0008
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#define HSMC3_MODE0 0x000c
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#define HSMC3_SETUP1 0x0010
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#define HSMC3_PULSE1 0x0014
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#define HSMC3_CYCLE1 0x0018
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#define HSMC3_MODE1 0x001c
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#define HSMC3_SETUP2 0x0020
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#define HSMC3_PULSE2 0x0024
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#define HSMC3_CYCLE2 0x0028
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#define HSMC3_MODE2 0x002c
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#define HSMC3_SETUP3 0x0030
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#define HSMC3_PULSE3 0x0034
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#define HSMC3_CYCLE3 0x0038
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#define HSMC3_MODE3 0x003c
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#define HSMC3_SETUP4 0x0040
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#define HSMC3_PULSE4 0x0044
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#define HSMC3_CYCLE4 0x0048
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#define HSMC3_MODE4 0x004c
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#define HSMC3_SETUP5 0x0050
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#define HSMC3_PULSE5 0x0054
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#define HSMC3_CYCLE5 0x0058
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#define HSMC3_MODE5 0x005c
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/* Bitfields in SETUP0 */
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#define HSMC3_NWE_SETUP_OFFSET 0
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#define HSMC3_NWE_SETUP_SIZE 6
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#define HSMC3_NCS_WR_SETUP_OFFSET 8
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#define HSMC3_NCS_WR_SETUP_SIZE 6
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#define HSMC3_NRD_SETUP_OFFSET 16
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#define HSMC3_NRD_SETUP_SIZE 6
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#define HSMC3_NCS_RD_SETUP_OFFSET 24
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#define HSMC3_NCS_RD_SETUP_SIZE 6
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/* Bitfields in PULSE0 */
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#define HSMC3_NWE_PULSE_OFFSET 0
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#define HSMC3_NWE_PULSE_SIZE 7
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#define HSMC3_NCS_WR_PULSE_OFFSET 8
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#define HSMC3_NCS_WR_PULSE_SIZE 7
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#define HSMC3_NRD_PULSE_OFFSET 16
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#define HSMC3_NRD_PULSE_SIZE 7
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#define HSMC3_NCS_RD_PULSE_OFFSET 24
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#define HSMC3_NCS_RD_PULSE_SIZE 7
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/* Bitfields in CYCLE0 */
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#define HSMC3_NWE_CYCLE_OFFSET 0
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#define HSMC3_NWE_CYCLE_SIZE 9
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#define HSMC3_NRD_CYCLE_OFFSET 16
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#define HSMC3_NRD_CYCLE_SIZE 9
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/* Bitfields in MODE0 */
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#define HSMC3_READ_MODE_OFFSET 0
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#define HSMC3_READ_MODE_SIZE 1
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#define HSMC3_WRITE_MODE_OFFSET 1
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#define HSMC3_WRITE_MODE_SIZE 1
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#define HSMC3_EXNW_MODE_OFFSET 4
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#define HSMC3_EXNW_MODE_SIZE 2
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#define HSMC3_BAT_OFFSET 8
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#define HSMC3_BAT_SIZE 1
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#define HSMC3_DBW_OFFSET 12
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#define HSMC3_DBW_SIZE 2
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#define HSMC3_TDF_CYCLES_OFFSET 16
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#define HSMC3_TDF_CYCLES_SIZE 4
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#define HSMC3_TDF_MODE_OFFSET 20
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#define HSMC3_TDF_MODE_SIZE 1
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#define HSMC3_PMEN_OFFSET 24
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#define HSMC3_PMEN_SIZE 1
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#define HSMC3_PS_OFFSET 28
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#define HSMC3_PS_SIZE 2
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/* Bitfields in MODE1 */
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#define HSMC3_PD_OFFSET 28
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#define HSMC3_PD_SIZE 2
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/* Constants for READ_MODE */
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#define HSMC3_READ_MODE_NCS_CONTROLLED 0
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#define HSMC3_READ_MODE_NRD_CONTROLLED 1
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/* Constants for WRITE_MODE */
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#define HSMC3_WRITE_MODE_NCS_CONTROLLED 0
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#define HSMC3_WRITE_MODE_NWE_CONTROLLED 1
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/* Constants for EXNW_MODE */
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#define HSMC3_EXNW_MODE_DISABLED 0
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#define HSMC3_EXNW_MODE_RESERVED 1
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#define HSMC3_EXNW_MODE_FROZEN 2
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#define HSMC3_EXNW_MODE_READY 3
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/* Constants for BAT */
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#define HSMC3_BAT_BYTE_SELECT 0
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#define HSMC3_BAT_BYTE_WRITE 1
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/* Constants for DBW */
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#define HSMC3_DBW_8_BITS 0
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#define HSMC3_DBW_16_BITS 1
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#define HSMC3_DBW_32_BITS 2
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/* Bit manipulation macros */
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#define HSMC3_BIT(name) \
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(1 << HSMC3_##name##_OFFSET)
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#define HSMC3_BF(name,value) \
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(((value) & ((1 << HSMC3_##name##_SIZE) - 1)) \
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<< HSMC3_##name##_OFFSET)
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#define HSMC3_BFEXT(name,value) \
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(((value) >> HSMC3_##name##_OFFSET) \
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& ((1 << HSMC3_##name##_SIZE) - 1))
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#define HSMC3_BFINS(name,value,old)\
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(((old) & ~(((1 << HSMC3_##name##_SIZE) - 1) \
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<< HSMC3_##name##_OFFSET)) \
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| HSMC3_BF(name,value))
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/* Register access macros */
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#define hsmc3_readl(reg) \
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readl((void *)ATMEL_BASE_HSMC + HSMC3_##reg)
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#define hsmc3_writel(reg,value) \
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writel((value), (void *)ATMEL_BASE_HSMC + HSMC3_##reg)
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#endif /* __CPU_AT32AP_HSMC3_H__ */
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