Marek Vasut 70ed80af46 ddr: altera: Zero DM IN delay in scc_mgr_zero_group() ...

This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>

2016-04-20 11:28:45 +02:00

..

Makefile

driver/ddr/altera: Add the sdram calibration portion

2015-08-08 14:14:05 +02:00

sdram.c

ddr: altera: Fix DRAM end value in protection rule

2016-04-20 11:28:44 +02:00

sequencer.c

ddr: altera: Zero DM IN delay in scc_mgr_zero_group()

2016-04-20 11:28:45 +02:00

sequencer.h

ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL

2015-08-08 14:14:29 +02:00