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c5c62155c5
Add a function comment for get_coreboot_info() and a declaration for cb_get_sysinfo(), since this may be called from elsewhere. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
237 lines
8.5 KiB
C
237 lines
8.5 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* This file is part of the libpayload project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*/
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#ifndef _COREBOOT_SYSINFO_H
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#define _COREBOOT_SYSINFO_H
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#include <asm/coreboot_tables.h>
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/* Maximum number of memory range definitions */
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#define SYSINFO_MAX_MEM_RANGES 32
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/* Allow a maximum of 8 GPIOs */
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#define SYSINFO_MAX_GPIOS 8
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/* Up to 10 MAC addresses */
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#define SYSINFO_MAX_MACS 10
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/**
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* struct sysinfo_t - Information passed to U-Boot from coreboot
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*
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* Coreboot passes on a lot of information using a list of individual data
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* structures identified by a numeric tag. These are parsed in U-Boot to produce
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* this struct. Some of the pointers here point back to the tagged data
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* structure, since it is assumed to remain around while U-Boot is running.
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*
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* The 'cbsysinfo' command can display this information.
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*
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* @cpu_khz: CPU frequence in KHz (e.g. 1100000)
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* @serial: Pointer to the serial information, NULL if none
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* @ser_ioport: Not actually provided by a tag and not used on modern hardware,
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* which typicaally uses a memory-mapped port
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* @ser_base: Not used at all, but present to match up with the coreboot data
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* structure
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* @n_memranges: Number of memory ranges
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* @memrange: List of memory ranges:
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* @base: Base address of range
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* @size: Size of range in bytes
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* @type: Type of range (CB_MEM_RAM, etc.)
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* @option_table: Provides a pointer to the CMOS RAM options table, which
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* indicates which options are available. The header is followed by a list
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* of struct cb_cmos_entries records, so that an option can be found from
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* its name. This is not used in U-Boot. NULL if not present
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* @cmos_range_start: Start bit of the CMOS checksum range (in fact this must
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* be a multiple of 8)
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* @cmos_range_end: End bit of the CMOS checksum range (multiple of 8). This is
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* the inclusive end.
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* @cmos_checksum_location: Location of checksum, multiplied by 8. This is the
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* byte offset into the CMOS RAM of the first checksum byte. The second one
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* follows immediately. The checksum is a simple 16-bit sum of all the
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* bytes from offset cmos_range_start / 8 to cmos_range_end / 8, inclusive,
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* in big-endian format (so sum >> 8 is stored in the first byte).
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* @vbnv_start: Start offset of CMOS RAM used for Chromium OS verified boot
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* (typically 0x34)
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* @vbnv_size: Number of bytes used by Chromium OS verified boot (typically
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* 0x10)
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* @extra_version: Extra version information, typically ""
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* @build: Build date, e.g. "Wed Nov 18 02:51:58 UTC 2020"
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* @compile_time: Compilation time, e.g. "02:51:58"
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* @compile_by: Who compiled coreboot (never set?)
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* @compile_host: Name of the machine that compiled coreboot (never set?)
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* @compile_domain: Domain name of the machine that compiled coreboot (never
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* set?)
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* @compiler: Name of the compiler used to build coreboot (never set?)
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* @linker: Name of the linker used to build coreboot (never set?)
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* @assembler: Name of the assembler used to build coreboot (never set?)
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* @cb_version: Coreboot version string, e.g. v1.9308_26_0.0.22-2599-g232f22c75d
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* @framebuffer: Address of framebuffer tag, or NULL if none. See
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* struct cb_framebuffer for the definition
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* @num_gpios: Number of verified-boot GPIOs
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* @gpios: List of GPIOs:
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* @port: GPIO number, or 0xffffffff if not a GPIO
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* @polarity: CB_GPIO_ACTIVE_LOW or CB_GPIO_ACTIVE_HIGH
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* @value: Value of GPIO (0 or 1)
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* @name: Name of GPIO
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*
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* A typical list is:
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* id: port polarity val name
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* 0: - active-high 1 write protect
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* 1: - active-high 0 recovery
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* 2: - active-high 1 lid
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* 3: - active-high 0 power
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* 4: - active-high 0 oprom
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* 5: 29 active-high 0 EC in RW
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*
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* @num_macs: Number of MAC addresses
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* @macs: List of MAC addresses
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* @serialno: Serial number, or NULL (never set?)
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* @mbtable: Address of the multiboot table, or NULL. This is a
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* struct multiboot_header, not used in U-Boot
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* @header: Address of header, if there is a CB_TAG_FORWARD, else NULL
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* @mainboard: Pointer to mainboard info or NULL. Typically the vendor is
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* "Google" and the part number is ""
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* @vboot_handoff: Pointer to Chromium OS verified boot hand-off information.
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* This is struct vboot_handoff, providing access to internal information
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* generated by coreboot when this is being used
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* @vboot_handoff_size: Size of hand-off information (typically 0xc0c)
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* @vdat_addr: Pointer to Chromium OS verified boot data, which uses
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* struct chromeos_acpi. It sits in the Intel Global NVS struct, after the
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* first 0x100 bytes
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* @vdat_size: Size of this data, typically 0xf00
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* @smbios_start: Address of SMBIOS tables
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* @smbios_size: Size of SMBIOS tables (e.g. 0x800)
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* @x86_rom_var_mtrr_index: MTRR number used for ROM caching. Not used in U-Boot
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* @tstamp_table: Pointer to timestamp_table, struct timestamp_table
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* @cbmem_cons: Pointer to the console dump, struct cbmem_console. This provides
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* access to the console output generated by coreboot, typically about 64KB
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* and mostly PCI enumeration info
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* @mrc_cache: Pointer to memory-reference-code cache, typically NULL
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* acpi_gnvs: @Pointer to Intel Global NVS struct, see struct acpi_global_nvs
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* @board_id: Board ID indicating the board variant, typically 0xffffffff
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* @ram_code: RAM code indicating the SDRAM type, typically 0xffffffff
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* @wifi_calibration: WiFi calibration info, NULL if none
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* @ramoops_buffer: Address of kernel Ramoops buffer
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* @ramoops_buffer_size: Sizeof of Ramoops buffer, typically 1MB
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* @spi_flash: Information about SPI flash:
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* @size: Size in bytes, e.g. 16MB
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* @sector_size; Sector size of flash device, e.g. 4KB
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* @erase_cmd: Command used to erase flash, or 0 if not used
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* @fmap_offset: SPI-flash offset of the flash map (FMAP) table. This has a
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* __FMAP__ header. It provides information about the different top-level
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* sections in the SPI flash, e.g. 0x204000
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* @cbfs_offset: SPI-flash offset of the Coreboot Filesystem (CBFS) used for
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* read-only data, e.g. 0x205000. This is typically called 'COREBOOT' in
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* the flash map. It holds various coreboot binaries as well as
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* video-configuration files and graphics data for the Chromium OS
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* verified boot user interface.
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* @cbfs_size: Size of CBFS, e.g. 0x17b000
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* @boot_media_size; Size of boot media (i.e. SPI flash), e.g. 16MB
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* @mtc_start; Start of MTC region (Nvidia private data), 0 if not used. See
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* https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeos-2013.04/src/soc/nvidia/tegra210/mtc.c
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* @mtc_size: Size of MTC region
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* @chromeos_vpd: Chromium OS Vital Product Data region, typically NULL, meaning
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* not used
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*/
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struct sysinfo_t {
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unsigned int cpu_khz;
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struct cb_serial *serial;
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unsigned short ser_ioport;
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unsigned long ser_base; // for mmapped serial
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int n_memranges;
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struct memrange {
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unsigned long long base;
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unsigned long long size;
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unsigned int type;
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} memrange[SYSINFO_MAX_MEM_RANGES];
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struct cb_cmos_option_table *option_table;
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u32 cmos_range_start;
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u32 cmos_range_end;
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u32 cmos_checksum_location;
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u32 vbnv_start;
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u32 vbnv_size;
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char *version;
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char *extra_version;
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char *build;
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char *compile_time;
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char *compile_by;
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char *compile_host;
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char *compile_domain;
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char *compiler;
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char *linker;
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char *assembler;
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char *cb_version;
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struct cb_framebuffer *framebuffer;
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int num_gpios;
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struct cb_gpio gpios[SYSINFO_MAX_GPIOS];
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int num_macs;
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struct mac_address macs[SYSINFO_MAX_MACS];
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char *serialno;
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unsigned long *mbtable; /** Pointer to the multiboot table */
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struct cb_header *header;
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struct cb_mainboard *mainboard;
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void *vboot_handoff;
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u32 vboot_handoff_size;
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void *vdat_addr;
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u32 vdat_size;
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u64 smbios_start;
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u32 smbios_size;
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int x86_rom_var_mtrr_index;
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void *tstamp_table;
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void *cbmem_cons;
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void *mrc_cache;
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void *acpi_gnvs;
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u32 board_id;
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u32 ram_code;
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void *wifi_calibration;
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u64 ramoops_buffer;
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u32 ramoops_buffer_size;
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struct {
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u32 size;
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u32 sector_size;
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u32 erase_cmd;
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} spi_flash;
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u64 fmap_offset;
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u64 cbfs_offset;
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u64 cbfs_size;
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u64 boot_media_size;
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u64 mtc_start;
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u32 mtc_size;
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void *chromeos_vpd;
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};
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extern struct sysinfo_t lib_sysinfo;
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/**
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* get_coreboot_info() - parse the coreboot sysinfo table
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*
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* Parses the coreboot table if found, setting the GD_FLG_SKIP_LL_INIT flag if
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* so.
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*
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* @info: Place to put the parsed information
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* @return 0 if OK, -ENOENT if no table found
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*/
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int get_coreboot_info(struct sysinfo_t *info);
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/**
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* cb_get_sysinfo() - get a pointer to the parsed coreboot sysinfo
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*
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* @return pointer to sysinfo, or NULL if not available
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*/
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const struct sysinfo_t *cb_get_sysinfo(void);
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#endif
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