York Sun 6c6e006a20 driver/ddr/fsl: Update timing config for heavy load ...

In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.

Signed-off-by: York Sun <yorksun@freescale.com>

2015-12-13 18:27:27 -08:00

..

altera

ddr: altera: Repair uninited variable

2015-08-23 11:56:19 +02:00

fsl

driver/ddr/fsl: Update timing config for heavy load

2015-12-13 18:27:27 -08:00

marvell

arm: mvebu: Fix SAR1_CPU_CORE_MASK

2015-11-17 23:41:41 +01:00