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6a4453ab06
Enable watchdog as early as possible after clock initialization which is set at 10 seconds. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
129 lines
2.8 KiB
C
129 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Intel Corporation <www.intel.com>
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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*
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*/
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#include <init.h>
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#include <log.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/utils.h>
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#include <hang.h>
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#include <image.h>
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#include <spl.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/firewall.h>
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#include <asm/arch/mailbox_s10.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <wdt.h>
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#include <dm/uclass.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 reset_flag(void)
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{
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/* Check rstmgr.stat for warm reset status */
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u32 status = readl(SOCFPGA_RSTMGR_ADDRESS);
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/* Check whether any L4 watchdogs or SDM had triggered warm reset */
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u32 warm_reset_mask = RSTMGR_L4WD_MPU_WARMRESET_MASK;
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if (status & warm_reset_mask)
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return 0;
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return 1;
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}
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void board_init_f(ulong dummy)
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{
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int ret;
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struct udevice *dev;
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/* Enable Async */
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asm volatile("msr daifclr, #4");
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#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_RECOVER_DATA_SECTION)
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spl_save_restore_data();
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#endif
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ret = spl_early_init();
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if (ret)
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hang();
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socfpga_get_managers_addr();
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/* Ensure watchdog is paused when debugging is happening */
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writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
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socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
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#ifdef CONFIG_HW_WATCHDOG
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/* Enable watchdog before initializing the HW */
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
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hw_watchdog_init();
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#endif
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/* ensure all processors are not released prior Linux boot */
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writeq(0, CPU_RELEASE_ADDR);
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timer_init();
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mbox_init();
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mbox_hps_stage_notify(HPS_EXECUTION_STATE_FSBL);
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sysmgr_pinmux_init();
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ret = uclass_get_device(UCLASS_CLK, 0, &dev);
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if (ret) {
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debug("Clock init failed: %d\n", ret);
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hang();
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}
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/*
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* Enable watchdog as early as possible before initializing other
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* component. Watchdog need to be enabled after clock driver because
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* it will retrieve the clock frequency from clock driver.
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*/
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if (CONFIG_IS_ENABLED(WDT))
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initr_watchdog();
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preloader_console_init();
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print_reset_info();
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cm_print_clock_quick_summary();
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ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-system-mgr-firewall", &dev);
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if (ret) {
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printf("System manager firewall configuration failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-l3interconnect-firewall", &dev);
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if (ret) {
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printf("L3 interconnect firewall configuration failed: %d\n", ret);
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hang();
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}
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ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
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if (ret) {
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debug("CCU init failed: %d\n", ret);
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hang();
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}
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#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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hang();
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}
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#endif
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#ifdef CONFIG_CADENCE_QSPI
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mbox_qspi_open();
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#endif
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}
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