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9945a30e2e
Add and use the correct number of ddr phy registers to update the
corresponding settings.
Fixes: cbf5c99ef3 ("board: phytec: common: Introduce a method to inject DDR timings deltas")
Signed-off-by: Dominik Haller <d.haller@phytec.de>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
70 lines
1.7 KiB
C
70 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2024 PHYTEC Messtechnik GmbH
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* Author: Wadim Egorov <w.egorov@phytec.de>
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*/
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#include "k3_ddrss_patch.h"
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#include <fdt_support.h>
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#include <linux/errno.h>
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#ifdef CONFIG_K3_AM64_DDRSS
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#define LPDDR4_INTR_CTL_REG_COUNT (423U)
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#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U)
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#define LPDDR4_INTR_PHY_REG_COUNT (1406U)
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#endif
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static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset,
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const char *name, uint32_t idx, u32 val)
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{
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val = cpu_to_be32(val);
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return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
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strlen(name),
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idx * sizeof(val), &val,
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sizeof(val));
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}
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int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss)
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{
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int i, j;
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int ret;
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int mem_offset;
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mem_offset = fdt_path_offset(fdt, "/memorycontroller@f300000");
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if (mem_offset < 0)
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return -ENODEV;
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for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
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for (j = 0; j < ddrss->ctl_regs_num; j++)
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if (i == ddrss->ctl_regs[j].off) {
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ret = fdt_setprop_inplace_idx_u32(fdt,
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mem_offset, "ti,ctl-data", i,
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ddrss->ctl_regs[j].val);
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if (ret)
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return ret;
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}
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for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
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for (j = 0; j < ddrss->pi_regs_num; j++)
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if (i == ddrss->pi_regs[j].off) {
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ret = fdt_setprop_inplace_idx_u32(fdt,
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mem_offset, "ti,pi-data", i,
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ddrss->pi_regs[j].val);
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if (ret)
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return ret;
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}
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for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
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for (j = 0; j < ddrss->phy_regs_num; j++)
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if (i == ddrss->phy_regs[j].off) {
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ret = fdt_setprop_inplace_idx_u32(fdt,
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mem_offset, "ti,phy-data", i,
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ddrss->phy_regs[j].val);
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if (ret)
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return ret;
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}
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return 0;
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}
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