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d3b9b79968
The phyCORE-i.MX 93 is available in various variants. Relevant variant options for the spl/u-boot are: - with or without HS400 support for the eMMC - with 1GB ram chip, or 2GB ram chip The phyCORE's eeprom contains all information about the existing variant options. Add evaluation of the eeprom data to the spl/u-boot to enable/disable HS400 and to select the appropriate ram configuration at startup. Signed-off-by: Christoph Stoidner <c.stoidner@phytec.de> Reviewed-by: Wadim Egorov <w.egorov@phytec.de> Reviewed-by: Yannic Moog <y.moog@phytec.de> Tested-by: Primoz Fiser <primoz.fiser@norik.com>
52 lines
1.4 KiB
C
52 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2024 PHYTEC Messtechnik GmbH
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* Author: Primoz Fiser <primoz.fiser@norik.com>
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*/
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#ifndef _PHYTEC_IMX93_SOM_DETECTION_H
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#define _PHYTEC_IMX93_SOM_DETECTION_H
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#include "phytec_som_detection.h"
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#define PHYTEC_IMX93_SOM 77
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enum phytec_imx93_option_index {
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PHYTEC_IMX93_OPT_DDR = 0,
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PHYTEC_IMX93_OPT_EMMC = 1,
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PHYTEC_IMX93_OPT_CPU = 2,
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PHYTEC_IMX93_OPT_FREQ = 3,
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PHYTEC_IMX93_OPT_NPU = 4,
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PHYTEC_IMX93_OPT_DISP = 5,
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PHYTEC_IMX93_OPT_ETH = 6,
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PHYTEC_IMX93_OPT_FEAT = 7,
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PHYTEC_IMX93_OPT_TEMP = 8,
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PHYTEC_IMX93_OPT_BOOT = 9,
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PHYTEC_IMX93_OPT_LED = 10,
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PHYTEC_IMX93_OPT_EEPROM = 11,
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};
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enum phytec_imx93_voltage {
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PHYTEC_IMX93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL,
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PHYTEC_IMX93_VOLTAGE_3V3 = 0,
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PHYTEC_IMX93_VOLTAGE_1V8 = 1,
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};
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enum phytec_imx93_ddr_eeprom_code {
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PHYTEC_IMX93_DDR_INVALID = PHYTEC_EEPROM_INVAL,
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PHYTEC_IMX93_LPDDR4X_512MB = 0,
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PHYTEC_IMX93_LPDDR4X_1GB = 1,
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PHYTEC_IMX93_LPDDR4X_2GB = 2,
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PHYTEC_IMX93_LPDDR4_512MB = 3,
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PHYTEC_IMX93_LPDDR4_1GB = 4,
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PHYTEC_IMX93_LPDDR4_2GB = 5,
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};
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u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data);
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u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data,
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enum phytec_imx93_option_index idx);
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enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage
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(struct phytec_eeprom_data *data);
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#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */
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