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47e544f576
Simon Glass <sjg@chromium.org> says: When the SPL build-phase was first created it was designed to solve a particular problem (the need to init SDRAM so that U-Boot proper could be loaded). It has since expanded to become an important part of U-Boot, with three phases now present: TPL, VPL and SPL Due to this history, the term 'SPL' is used to mean both a particular phase (the one before U-Boot proper) and all the non-proper phases. This has become confusing. For a similar reason CONFIG_SPL_BUILD is set to 'y' for all 'SPL' phases, not just SPL. So code which can only be compiled for actual SPL, for example, must use something like this: #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD) In Makefiles we have similar issues. SPL_ has been used as a variable which expands to either SPL_ or nothing, to chose between options like CONFIG_BLK and CONFIG_SPL_BLK. When TPL appeared, a new SPL_TPL variable was created which expanded to 'SPL_', 'TPL_' or nothing. Later it was updated to support 'VPL_' as well. This series starts a change in terminology and usage to resolve the above issues: - The word 'xPL' is used instead of 'SPL' to mean a non-proper build - A new CONFIG_XPL_BUILD define indicates that the current build is an 'xPL' build - The existing CONFIG_SPL_BUILD is changed to mean SPL; it is not now defined for TPL and VPL phases - The existing SPL_ Makefile variable is renamed to SPL_ - The existing SPL_TPL Makefile variable is renamed to PHASE_ It should be noted that xpl_phase() can generally be used instead of the above CONFIGs without a code-space or run-time penalty. This series does not attempt to convert all of U-Boot to use this new terminology but it makes a start. In particular, renaming spl.h and common/spl seems like a bridge too far at this point. The series is fully bisectable. It has also been checked to ensure there are no code-size changes on any commit.
90 lines
2.0 KiB
C
90 lines
2.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2015 Google, Inc
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*/
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#include <clk.h>
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#include <dm.h>
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#include <init.h>
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#include <log.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/global_data.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <power/regulator.h>
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/*
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* We should increase the DDR voltage to 1.2V using the PWM regulator.
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* There is a U-Boot driver for this but it may need to add support for the
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* 'voltage-table' property.
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*/
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#ifndef CONFIG_XPL_BUILD
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#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
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static int veyron_init(void)
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{
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struct udevice *dev;
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struct clk clk;
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int ret;
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ret = regulator_get_by_platname("vdd_arm", &dev);
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if (ret)
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return log_msg_ret("vdd", ret);
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/* Slowly raise to max CPU voltage to prevent overshoot */
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ret = regulator_set_value(dev, 1200000);
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if (ret)
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return log_msg_ret("s12", ret);
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udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
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ret = regulator_set_value(dev, 1400000);
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if (ret)
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return log_msg_ret("s14", ret);
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udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
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ret = rockchip_get_clk(&clk.dev);
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if (ret)
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return log_msg_ret("clk", ret);
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clk.id = PLL_APLL;
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ret = clk_set_rate(&clk, 1800000000);
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if (IS_ERR_VALUE(ret))
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return log_msg_ret("s18", ret);
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ret = regulator_get_by_platname("vcc33_sd", &dev);
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if (ret)
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return log_msg_ret("vcc", ret);
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ret = regulator_set_value(dev, 3300000);
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if (ret)
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return log_msg_ret("s33", ret);
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return 0;
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}
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#endif
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int board_early_init_r(void)
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{
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struct udevice *dev;
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int ret;
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#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
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if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
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ret = veyron_init();
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if (ret)
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return log_msg_ret("vey", ret);
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}
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#endif
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/*
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* This init is done in SPL, but when chain-loading U-Boot SPL will
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* have been skipped. Allow the clock driver to check if it needs
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* setting up.
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*/
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ret = rockchip_get_clk(&dev);
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if (ret) {
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debug("CLK init failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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#endif
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