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bfc8ca3f7f
Add insn-def.h which is similar to that in linux and contains the macros to generate any instruction of type 'I' using the assembler's .insn directive. Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
40 lines
1.0 KiB
C
40 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2024 Ventana Micro Systems Ltd.
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*
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* Ported from linux insn-def.h.
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*/
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#ifndef _ASM_RISCV_BARRIER_H
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#define _ASM_RISCV_BARRIER_H
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#define INSN_I_SIMM12_SHIFT 20
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#define INSN_I_RS1_SHIFT 15
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#define INSN_I_FUNC3_SHIFT 12
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#define INSN_I_RD_SHIFT 7
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#define INSN_I_OPCODE_SHIFT 0
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#define RV_OPCODE(v) __ASM_STR(v)
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#define RV_FUNC3(v) __ASM_STR(v)
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#define RV_FUNC7(v) __ASM_STR(v)
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#define RV_SIMM12(v) __ASM_STR(v)
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#define RV_RD(v) __ASM_STR(v)
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#define RV_RS1(v) __ASM_STR(v)
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#define RV_RS2(v) __ASM_STR(v)
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#define __RV_REG(v) __ASM_STR(x ## v)
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#define RV___RD(v) __RV_REG(v)
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#define RV___RS1(v) __RV_REG(v)
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#define RV___RS2(v) __RV_REG(v)
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#define RV_OPCODE_MISC_MEM RV_OPCODE(15)
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#define RV_OPCODE_SYSTEM RV_OPCODE(115)
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#define __INSN_I(opcode, func3, rd, rs1, simm12) \
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".insn i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n"
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#define INSN_I(opcode, func3, rd, rs1, simm12) \
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__INSN_I(RV_##opcode, RV_##func3, RV_##rd, \
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RV_##rs1, RV_##simm12)
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#endif /* _ASM_RISCV_BARRIER_H */
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