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42276c3658
Caleb Connolly <caleb.connolly@linaro.org> says:
MMU issues are some of the most frustrating to debug. To make this
slightly less unbearable, introduce a software pagetable walker for
ARMv8. This can be called to dump a pagetable with the default
formatter, or a custom callback can be provided to implement more
complicated parsing.
This can also be useful to dump the pagetable used by a previous
bootloader stage (by reading out the ttbr register).
Here is an example of the output when walking U-Boot's own memory map
on a Qualcomm RB3 board:
Walking pagetable at 000000017df90000, va_bits: 36. Using 3 levels
[0x17df91000] | Table | |
[0x17df92000] | Table | |
[0x000001000 - 0x000200000] | Pages | Device-nGnRnE | Non-shareable
[0x000200000 - 0x040000000] | Block | Device-nGnRnE | Non-shareable
[0x040000000 - 0x080000000] | Block | Device-nGnRnE | Non-shareable
[0x080000000 - 0x140000000] | Block | Normal | Inner-shareable
[0x17df93000] | Table | |
[0x140000000 - 0x17de00000] | Block | Normal | Inner-shareable
[0x17df94000] | Table | |
[0x17de00000 - 0x17dfa0000] | Pages | Normal | Inner-shareable
201 lines
5.3 KiB
C
201 lines
5.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*/
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#ifndef _ASM_ARMV8_MMU_H_
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#define _ASM_ARMV8_MMU_H_
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#include <hang.h>
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#include <linux/const.h>
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/*
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* block/section address mask and size definitions.
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*/
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/* PAGE_SHIFT determines the page size */
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#undef PAGE_SIZE
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (1 << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE - 1))
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/***************************************************************/
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/*
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* Memory types
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*/
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#define MT_DEVICE_NGNRNE 0
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#define MT_DEVICE_NGNRE 1
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#define MT_DEVICE_GRE 2
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#define MT_NORMAL_NC 3
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#define MT_NORMAL 4
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#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE * 8)) | \
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(0x04 << (MT_DEVICE_NGNRE * 8)) | \
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(0x0c << (MT_DEVICE_GRE * 8)) | \
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(0x44 << (MT_NORMAL_NC * 8)) | \
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(UL(0xff) << (MT_NORMAL * 8)))
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/*
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* Hardware page table definitions.
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*
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*/
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#define PTE_TYPE_MASK (3 << 0)
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#define PTE_TYPE_FAULT (0 << 0)
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#define PTE_TYPE_TABLE (3 << 0)
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#define PTE_TYPE_PAGE (3 << 0)
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#define PTE_TYPE_BLOCK (1 << 0)
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#define PTE_TYPE_VALID (1 << 0)
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#define PTE_TABLE_PXN (1UL << 59)
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#define PTE_TABLE_XN (1UL << 60)
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#define PTE_TABLE_AP (3UL << 61)
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#define PTE_TABLE_NS (1UL << 63)
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/*
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* Block
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*/
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#define PTE_BLOCK_MEMTYPE(x) ((x) << 2)
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#define PTE_BLOCK_NS (1 << 5)
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#define PTE_BLOCK_NON_SHARE (0 << 8)
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#define PTE_BLOCK_OUTER_SHARE (2 << 8)
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#define PTE_BLOCK_INNER_SHARE (3 << 8)
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#define PTE_BLOCK_AF (1 << 10)
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#define PTE_BLOCK_NG (1 << 11)
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#define PTE_BLOCK_PXN (UL(1) << 53)
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#define PTE_BLOCK_UXN (UL(1) << 54)
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/*
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* AttrIndx[2:0]
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*/
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#define PMD_ATTRINDX(t) ((t) << 2)
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#define PMD_ATTRINDX_MASK (7 << 2)
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#define PMD_ATTRMASK (PTE_BLOCK_PXN | \
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PTE_BLOCK_UXN | \
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PMD_ATTRINDX_MASK | \
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PTE_TYPE_VALID)
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/*
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* TCR flags.
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*/
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#define TCR_T0SZ(x) ((64 - (x)) << 0)
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#define TCR_IRGN_NC (0 << 8)
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#define TCR_IRGN_WBWA (1 << 8)
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#define TCR_IRGN_WT (2 << 8)
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#define TCR_IRGN_WBNWA (3 << 8)
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#define TCR_IRGN_MASK (3 << 8)
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#define TCR_ORGN_NC (0 << 10)
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#define TCR_ORGN_WBWA (1 << 10)
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#define TCR_ORGN_WT (2 << 10)
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#define TCR_ORGN_WBNWA (3 << 10)
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#define TCR_ORGN_MASK (3 << 10)
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#define TCR_SHARED_NON (0 << 12)
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#define TCR_SHARED_OUTER (2 << 12)
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#define TCR_SHARED_INNER (3 << 12)
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#define TCR_TG0_4K (0 << 14)
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#define TCR_TG0_64K (1 << 14)
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#define TCR_TG0_16K (2 << 14)
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#define TCR_EPD1_DISABLE (1 << 23)
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#define TCR_EL1_RSVD (1U << 31)
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#define TCR_EL2_RSVD (1U << 31 | 1 << 23)
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#define TCR_EL3_RSVD (1U << 31 | 1 << 23)
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#define HCR_EL2_E2H_BIT 34
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
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{
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asm volatile("dsb sy");
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if (el == 1) {
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asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
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asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
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asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
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} else if (el == 2) {
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asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
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asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
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asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
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} else if (el == 3) {
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asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
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asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
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asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
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} else {
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hang();
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}
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asm volatile("isb");
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}
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static inline void get_ttbr_tcr_mair(int el, u64 *table, u64 *tcr, u64 *attr)
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{
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if (el == 1) {
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asm volatile("mrs %0, ttbr0_el1" : "=r" (*table));
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asm volatile("mrs %0, tcr_el1" : "=r" (*tcr));
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asm volatile("mrs %0, mair_el1" : "=r" (*attr));
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} else if (el == 2) {
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asm volatile("mrs %0, ttbr0_el2" : "=r" (*table));
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asm volatile("mrs %0, tcr_el2" : "=r" (*tcr));
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asm volatile("mrs %0, mair_el2" : "=r" (*attr));
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} else if (el == 3) {
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asm volatile("mrs %0, ttbr0_el3" : "=r" (*table));
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asm volatile("mrs %0, tcr_el3" : "=r" (*tcr));
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asm volatile("mrs %0, mair_el3" : "=r" (*attr));
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} else {
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hang();
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}
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}
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/**
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* typedef pte_walker_cb_t - callback function for walk_pagetable.
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*
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* This function is called when the walker finds a table entry
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* or after parsing a block or pages. For a table the @end address
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* is 0, and @addr is the address of the table. Otherwise, they
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* are the start and end physical addresses of the block or page.
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*
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* @addr: PTE start address (PA), or address of table. Includes attributes.
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* @end: End address of the region (or 0 for a table)
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* @va_bits: Number of bits in the virtual address
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* @level: Table level
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* @priv: Private data for the callback
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*
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* Return: true to stop walking, false to continue
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*/
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typedef bool (*pte_walker_cb_t)(u64 addr, u64 end, int va_bits, int level, void *priv);
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/**
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* walk_pagetable() - Walk the pagetable at ttbr and call @cb for each region
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*
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* @ttbr: Address of the pagetable to dump
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* @tcr: TCR value to use
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* @cb: Callback function to call for each entry
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* @priv: Private data for the callback
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*/
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void walk_pagetable(u64 ttbr, u64 tcr, pte_walker_cb_t cb, void *priv);
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/**
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* dump_pagetable() - Dump the pagetable at ttbr, printing each region and
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* level.
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*
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* @ttbr: Address of the pagetable to dump
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* @tcr: TCR value to use
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*/
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void dump_pagetable(u64 ttbr, u64 tcr);
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struct mm_region {
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u64 virt;
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u64 phys;
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u64 size;
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u64 attrs;
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};
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extern struct mm_region *mem_map;
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void setup_pgtables(void);
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u64 get_tcr(u64 *pips, u64 *pva_bits);
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#endif
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#endif /* _ASM_ARMV8_MMU_H_ */
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