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2fca3cf799
Add MIDR entries for Cortex-A57 and Cortex-A76 cores. Those are used on R-Car Gen3 and Gen4 SoCs respectively. Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com> Reviewed-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
37 lines
810 B
C
37 lines
810 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2018 NXP
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*/
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#define MIDR_PARTNUM_CORTEX_A35 0xD04
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#define MIDR_PARTNUM_CORTEX_A53 0xD03
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#define MIDR_PARTNUM_CORTEX_A57 0xD07
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#define MIDR_PARTNUM_CORTEX_A72 0xD08
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#define MIDR_PARTNUM_CORTEX_A76 0xD0B
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#define MIDR_PARTNUM_SHIFT 0x4
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#define MIDR_PARTNUM_MASK (0xFFF << MIDR_PARTNUM_SHIFT)
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static inline unsigned int read_midr(void)
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{
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unsigned long val;
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asm volatile("mrs %0, midr_el1" : "=r" (val));
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return val;
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}
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#define is_cortex_a(__n) \
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static inline int is_cortex_a##__n(void) \
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{ \
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unsigned int midr = read_midr(); \
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midr &= MIDR_PARTNUM_MASK; \
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midr >>= MIDR_PARTNUM_SHIFT; \
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return midr == MIDR_PARTNUM_CORTEX_A##__n; \
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}
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is_cortex_a(35)
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is_cortex_a(53)
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is_cortex_a(57)
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is_cortex_a(72)
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is_cortex_a(76)
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