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https://source.denx.de/u-boot/u-boot.git
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a9d562daa3
iMX91 is reduced part from iMX93 with part number: i.MX9131/11/01 It removed A55_1, M33, MIPI DSI, LVDS, etc. i.MX9131: - Support 2.4GT/s DDR and HWFFC at 1.2GT/s i.MX9121: - A55 at 800Mhz and DDR at 1600MTS, with low drive mode. i.MX9111: - Support 1.6GT/s DDR and HWFFC at 800MT/s i.MX9101: - Support 800Mhz ARM clock - Support 1.6GT/s DDR and HWFFC at 800MT/s - No parallel display, eQOS, flexcan Updated Clock/Container/CPU and etc for i.MX91 Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
119 lines
3.8 KiB
C
119 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#define MXC_CPU_MX23 0x23
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#define MXC_CPU_MX25 0x25
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#define MXC_CPU_MX27 0x27
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#define MXC_CPU_MX28 0x28
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#define MXC_CPU_MX31 0x31
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#define MXC_CPU_MX35 0x35
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#define MXC_CPU_MX51 0x51
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#define MXC_CPU_MX53 0x53
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#define MXC_CPU_MX6SL 0x60
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#define MXC_CPU_MX6DL 0x61
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#define MXC_CPU_MX6SX 0x62
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#define MXC_CPU_MX6Q 0x63
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#define MXC_CPU_MX6UL 0x64
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#define MXC_CPU_MX6ULL 0x65
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#define MXC_CPU_MX6ULZ 0x6B
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#define MXC_CPU_MX6SOLO 0x66 /* dummy */
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#define MXC_CPU_MX6SLL 0x67
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#define MXC_CPU_MX6D 0x6A
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#define MXC_CPU_MX6DP 0x68
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#define MXC_CPU_MX6QP 0x69
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#define MXC_CPU_MX7S 0x71 /* dummy ID */
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#define MXC_CPU_MX7D 0x72
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#define MXC_CPU_IMX8MQ 0x82
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#define MXC_CPU_IMX8MD 0x83 /* dummy ID */
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#define MXC_CPU_IMX8MQL 0x84 /* dummy ID */
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#define MXC_CPU_IMX8MM 0x85 /* dummy ID */
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#define MXC_CPU_IMX8MML 0x86 /* dummy ID */
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#define MXC_CPU_IMX8MMD 0x87 /* dummy ID */
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#define MXC_CPU_IMX8MMDL 0x88 /* dummy ID */
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#define MXC_CPU_IMX8MMS 0x89 /* dummy ID */
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#define MXC_CPU_IMX8MMSL 0x8a /* dummy ID */
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#define MXC_CPU_IMX8MN 0x8b /* dummy ID */
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#define MXC_CPU_IMX8MND 0x8c /* dummy ID */
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#define MXC_CPU_IMX8MNS 0x8d /* dummy ID */
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#define MXC_CPU_IMX8MNL 0x8e /* dummy ID */
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#define MXC_CPU_IMX8MNDL 0x8f /* dummy ID */
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#define MXC_CPU_IMX8MNSL 0x181 /* dummy ID */
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#define MXC_CPU_IMX8MNUQ 0x182 /* dummy ID */
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#define MXC_CPU_IMX8MNUD 0x183 /* dummy ID */
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#define MXC_CPU_IMX8MNUS 0x184 /* dummy ID */
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#define MXC_CPU_IMX8MP 0x185/* dummy ID */
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#define MXC_CPU_IMX8MP6 0x186 /* dummy ID */
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#define MXC_CPU_IMX8MPL 0x187 /* dummy ID */
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#define MXC_CPU_IMX8MPD 0x188 /* dummy ID */
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#define MXC_CPU_IMX8MPUL 0x189 /* dummy ID */
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#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
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#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
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#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
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#define MXC_CPU_IMX8ULP 0xA1 /* dummy ID */
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#define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */
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#define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */
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#define MXC_CPU_IMXRT1170 0xBA /* dummy ID */
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#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
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#define MXC_CPU_VF610 0xF6 /* dummy ID */
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#define MXC_CPU_IMX93 0xC1 /* dummy ID */
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#define MXC_CPU_IMX9351 0xC2 /* dummy ID */
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#define MXC_CPU_IMX9332 0xC3 /* dummy ID */
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#define MXC_CPU_IMX9331 0xC4 /* dummy ID */
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#define MXC_CPU_IMX9322 0xC5 /* dummy ID */
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#define MXC_CPU_IMX9321 0xC6 /* dummy ID */
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#define MXC_CPU_IMX9312 0xC7 /* dummy ID */
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#define MXC_CPU_IMX9311 0xC8 /* dummy ID */
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#define MXC_CPU_IMX9302 0xC9 /* dummy ID */
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#define MXC_CPU_IMX9301 0xCA /* dummy ID */
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#define MXC_CPU_IMX91 0xCB /* dummy ID */
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#define MXC_CPU_IMX9121 0xCC /* dummy ID */
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#define MXC_CPU_IMX9111 0xCD /* dummy ID */
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#define MXC_CPU_IMX9101 0xCE /* dummy ID */
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#define MXC_SOC_MX6 0x60
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#define MXC_SOC_MX7 0x70
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#define MXC_SOC_IMX8M 0x80
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#define MXC_SOC_IMX8 0x90 /* dummy */
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#define MXC_SOC_IMXRT 0xB0 /* dummy */
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#define MXC_SOC_MX7ULP 0xE0 /* dummy */
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#define MXC_SOC_IMX9 0xC0 /* dummy */
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#define CHIP_REV_1_0 0x10
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#define CHIP_REV_1_1 0x11
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#define CHIP_REV_1_2 0x12
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#define CHIP_REV_1_3 0x13
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#define CHIP_REV_1_5 0x15
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#define CHIP_REV_2_0 0x20
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#define CHIP_REV_2_1 0x21
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#define CHIP_REV_2_2 0x22
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#define CHIP_REV_2_5 0x25
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#define CHIP_REV_3_0 0x30
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#define CHIP_REV_A 0x0
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#define CHIP_REV_B 0x1
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#define CHIP_REV_C 0x2
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#define BOARD_REV_1_0 0x0
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#define BOARD_REV_2_0 0x1
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#define BOARD_VER_OFFSET 0x8
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#define CS0_128 0
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#define CS0_64M_CS1_64M 1
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#define CS0_64M_CS1_32M_CS2_32M 2
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#define CS0_32M_CS1_32M_CS2_32M_CS3_32M 3
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u32 get_imx_reset_cause(void);
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ulong get_systemPLLCLK(void);
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ulong get_FCLK(void);
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ulong get_HCLK(void);
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ulong get_BCLK(void);
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ulong get_PERCLK1(void);
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ulong get_PERCLK2(void);
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ulong get_PERCLK3(void);
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