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ca610ddf97
This patch adds GPIO controller driver for MediaTek MT7620 SoC Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
147 lines
3.3 KiB
C
147 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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*
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* GPIO controller driver for MediaTek MT7620 SoC
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*/
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#include <dm.h>
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#include <errno.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <asm/gpio.h>
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enum mt7620_regs {
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GPIO_REG_DATA,
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GPIO_REG_DIR,
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GPIO_REG_SET,
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GPIO_REG_CLR,
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__GPIO_REG_MAX
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};
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struct mt7620_gpio_priv {
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void __iomem *base;
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u32 regs[__GPIO_REG_MAX];
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u32 count;
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};
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static int mt7620_gpio_get_value(struct udevice *dev, unsigned int offset)
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{
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struct mt7620_gpio_priv *priv = dev_get_priv(dev);
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return !!(readl(priv->base + priv->regs[GPIO_REG_DATA]) & BIT(offset));
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}
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static int mt7620_gpio_set_value(struct udevice *dev, unsigned int offset,
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int value)
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{
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struct mt7620_gpio_priv *priv = dev_get_priv(dev);
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u32 reg;
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reg = value ? priv->regs[GPIO_REG_SET] : priv->regs[GPIO_REG_CLR];
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writel(BIT(offset), priv->base + reg);
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return 0;
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}
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static int mt7620_gpio_direction_input(struct udevice *dev, unsigned int offset)
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{
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struct mt7620_gpio_priv *priv = dev_get_priv(dev);
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clrbits_32(priv->base + priv->regs[GPIO_REG_DIR], BIT(offset));
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return 0;
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}
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static int mt7620_gpio_direction_output(struct udevice *dev,
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unsigned int offset, int value)
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{
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struct mt7620_gpio_priv *priv = dev_get_priv(dev);
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/* Set value first */
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mt7620_gpio_set_value(dev, offset, value);
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setbits_32(priv->base + priv->regs[GPIO_REG_DIR], BIT(offset));
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return 0;
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}
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static int mt7620_gpio_get_function(struct udevice *dev, unsigned int offset)
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{
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struct mt7620_gpio_priv *priv = dev_get_priv(dev);
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return (readl(priv->base + priv->regs[GPIO_REG_DIR]) & BIT(offset)) ?
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GPIOF_OUTPUT : GPIOF_INPUT;
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}
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static const struct dm_gpio_ops mt7620_gpio_ops = {
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.direction_input = mt7620_gpio_direction_input,
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.direction_output = mt7620_gpio_direction_output,
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.get_value = mt7620_gpio_get_value,
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.set_value = mt7620_gpio_set_value,
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.get_function = mt7620_gpio_get_function,
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};
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static int mt7620_gpio_probe(struct udevice *dev)
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{
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struct mt7620_gpio_priv *priv = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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const char *name;
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name = dev_read_string(dev, "mediatek,bank-name");
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if (!name)
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name = dev->name;
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uc_priv->gpio_count = priv->count;
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uc_priv->bank_name = name;
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return 0;
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}
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static int mt7620_gpio_of_to_plat(struct udevice *dev)
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{
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struct mt7620_gpio_priv *priv = dev_get_priv(dev);
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int ret;
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priv->base = dev_remap_addr_index(dev, 0);
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if (!priv->base) {
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dev_err(dev, "mt7620_gpio: unable to map registers\n");
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return -EINVAL;
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}
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ret = dev_read_u32(dev, "mediatek,gpio-num", &priv->count);
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if (ret) {
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dev_err(dev, "mt7620_gpio: failed to get GPIO count\n");
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return -EINVAL;
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}
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ret = dev_read_u32_array(dev, "mediatek,register-map", priv->regs,
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__GPIO_REG_MAX);
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if (ret) {
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dev_err(dev, "mt7620_gpio: unable to get register map\n");
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return -EINVAL;
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}
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return 0;
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}
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static const struct udevice_id mt7620_gpio_ids[] = {
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{ .compatible = "mediatek,mt7620-gpio" },
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{ }
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};
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U_BOOT_DRIVER(mt7620_gpio) = {
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.name = "mt7620_gpio",
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.id = UCLASS_GPIO,
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.ops = &mt7620_gpio_ops,
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.of_match = mt7620_gpio_ids,
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.probe = mt7620_gpio_probe,
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.of_to_plat = mt7620_gpio_of_to_plat,
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.priv_auto = sizeof(struct mt7620_gpio_priv),
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};
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