York Sun 66869f9554 drivers/ddr/fsl: Update DDR driver for DDR4 ...

Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.

Signed-off-by: York Sun <yorksun@freescale.com>

2015-04-23 08:55:53 -07:00

..

fsl

drivers/ddr/fsl: Update DDR driver for DDR4

2015-04-23 08:55:53 -07:00

mvebu

arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr

2015-02-06 17:25:03 +01:00