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Configure RMMI and M-PHY registers for HS mode required for selection of bit rate series A or B. If it is not a calibrated part, then switch back to SLOWAUTO_MODE and skip all these configurations. Implemented below sequence as per the DWC RMMI databook. 1. Override RMMI CBRATESEL with the desired rate. 2. Set TX_CFGUPDT_0 to 1'b1 for one TX_CFGCLK_0 cycle. 3. Override PHY rx_req to 1, then poll on PHY rx_ack register till it goes 1(both lanes). 4. Override PHY rx_req to 0, then poll on PHY rx_ack register till it goes 0(both lanes). 5. Remove PHY rx_req override(both lanes). 6. Start the LS PMC. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250724044402.260149-1-venkatesh.abbarapu@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>