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b4b266fc13
The MediaTek MT7987/MT7988 SoCs features a built-in 2.5Gb PHY
connected to GMAC1. The PHY supports 10/100/1000/2500 Mbps
full-duplex only.
The PHY requires one or two firmware files. Firmware for MT7988 has
already been added to upstream: mediatek/mt7988/i2p5ge-phy-pmb.bin.
MT7987 has two firmware files which will be add to upstream later:
i2p5ge-phy-pmb.bin and i2p5ge-phy-DSPBitTb.bin.
Environment variable can be set for firmware data loading:
mt7987_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
mt7987_i2p5ge_load_dspbit_firmware for i2p5ge-phy-DSPBitTb.bin
mt7988_i2p5ge_load_pmb_firmware for i2p5ge-phy-pmb.bin
This driver allows dedicated weak functions to be overridden by
board to provide the firmware data:
mt7987_i2p5ge_get_fw() for MT7987
mt7988_i2p5ge_get_fw() for MT7988
To enable the PHY, add the following not to device tree:
ð1 {
status = "okay";
phy-mode = "xgmii";
phy-handle = <&phy15>;
phy15: ethernet-phy@15 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <15>;
phy-mode = "xgmii";
};
};
Signed-off-by: Sky Huang <SkyLake.Huang@mediatek.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
107 lines
3.1 KiB
C
107 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2025 MediaTek Inc. All Rights Reserved.
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*
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* Author: Sky Huang <SkyLake.Huang@mediatek.com>
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*/
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#include <dm/device_compat.h>
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#include <phy.h>
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#include "mtk.h"
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void mtk_phy_select_page(struct phy_device *phydev, int page)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, MTK_EXT_PAGE_ACCESS, page);
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}
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void mtk_phy_restore_page(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, MTK_EXT_PAGE_ACCESS,
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MTK_PHY_PAGE_STANDARD);
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}
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/* Difference between functions with mtk_tr* and __mtk_tr* prefixes is
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* mtk_tr* functions: wrapped by page switching operations
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* __mtk_tr* functions: no page switching operations
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*/
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static void __mtk_tr_access(struct phy_device *phydev, bool read, u8 ch_addr,
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u8 node_addr, u8 data_addr)
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{
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u16 tr_cmd = BIT(15); /* bit 14 & 0 are reserved */
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if (read)
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tr_cmd |= BIT(13);
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tr_cmd |= (((ch_addr & 0x3) << 11) |
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((node_addr & 0xf) << 7) |
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((data_addr & 0x3f) << 1));
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dev_dbg(phydev->dev, "tr_cmd: 0x%x\n", tr_cmd);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x10, tr_cmd);
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}
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static void __mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr, u16 *tr_high, u16 *tr_low)
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{
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__mtk_tr_access(phydev, true, ch_addr, node_addr, data_addr);
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*tr_low = phy_read(phydev, MDIO_DEVAD_NONE, 0x11);
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*tr_high = phy_read(phydev, MDIO_DEVAD_NONE, 0x12);
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dev_dbg(phydev->dev, "tr_high read: 0x%x, tr_low read: 0x%x\n",
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*tr_high, *tr_low);
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}
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u32 mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr)
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{
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u16 tr_high;
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u16 tr_low;
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mtk_phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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__mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low);
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mtk_phy_restore_page(phydev);
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return (tr_high << 16) | tr_low;
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}
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static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr, u32 tr_data)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, 0x11, tr_data & 0xffff);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x12, tr_data >> 16);
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dev_dbg(phydev->dev, "tr_high write: 0x%x, tr_low write: 0x%x\n",
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tr_data >> 16, tr_data & 0xffff);
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__mtk_tr_access(phydev, false, ch_addr, node_addr, data_addr);
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}
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void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr, u32 mask, u32 set)
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{
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u32 tr_data;
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u16 tr_high;
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u16 tr_low;
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__mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low);
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tr_data = (tr_high << 16) | tr_low;
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tr_data = (tr_data & ~mask) | set;
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__mtk_tr_write(phydev, ch_addr, node_addr, data_addr, tr_data);
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}
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void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr, u32 mask, u32 set)
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{
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mtk_phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
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__mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, mask, set);
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mtk_phy_restore_page(phydev);
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}
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void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr, u32 set)
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{
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__mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, 0, set);
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}
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void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
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u8 data_addr, u32 clr)
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{
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__mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, clr, 0);
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}
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