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Add a driver for the PCA9541 i2c bus arbitrator based on the Linux driver for the same device. Co-developed-by: Jonathan Stroud <jonathan.stroud@amd.com> Signed-off-by: Jonathan Stroud <jonathan.stroud@amd.com> Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
298 lines
7.7 KiB
C
298 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2008-2009 Rodolfo Giometti <giometti@linux.it>
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* Copyright (c) 2008-2009 Eurotech S.p.A. <info@eurotech.it>
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* Copyright (c) 2010 Ericsson AB.
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* Copyright (c) 2025 Advanced Micro Devices, Inc.
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*/
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#include <dm.h>
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#include <errno.h>
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#include <i2c.h>
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#include <log.h>
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#include <malloc.h>
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#include <linux/delay.h>
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/*
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* The PCA9541 is a bus master selector. It supports two I2C masters connected
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* to a single slave bus.
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*
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* Before each bus transaction, a master has to acquire bus ownership. After the
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* transaction is complete, bus ownership has to be released. This fits well
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* into the I2C multiplexer framework, which provides select and release
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* functions for this purpose. For this reason, this driver is modeled as
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* single-channel I2C bus multiplexer.
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*
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* This driver assumes that the two bus masters are controlled by two different
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* hosts. If a single host controls both masters, platform code has to ensure
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* that only one of the masters is instantiated at any given time.
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*/
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#define PCA9541_CONTROL 0x01
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#define PCA9541_ISTAT 0x02
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#define PCA9541_CTL_MYBUS BIT(0)
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#define PCA9541_CTL_NMYBUS BIT(1)
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#define PCA9541_CTL_BUSON BIT(2)
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#define PCA9541_CTL_NBUSON BIT(3)
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#define PCA9541_CTL_BUSINIT BIT(4)
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#define PCA9541_CTL_TESTON BIT(6)
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#define PCA9541_CTL_NTESTON BIT(7)
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#define PCA9541_ISTAT_INTIN BIT(0)
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#define PCA9541_ISTAT_BUSINIT BIT(1)
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#define PCA9541_ISTAT_BUSOK BIT(2)
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#define PCA9541_ISTAT_BUSLOST BIT(3)
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#define PCA9541_ISTAT_MYTEST BIT(6)
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#define PCA9541_ISTAT_NMYTEST BIT(7)
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#define BUSON (PCA9541_CTL_BUSON | PCA9541_CTL_NBUSON)
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#define MYBUS (PCA9541_CTL_MYBUS | PCA9541_CTL_NMYBUS)
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/* arbitration timeouts, in jiffies */
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#define ARB_TIMEOUT_US 125000 /* 125 ms until forcing bus ownership */
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#define ARB2_TIMEOUT_US 250000 /* 250 ms until acquisition failure */
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/* arbitration retry delays, in us */
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#define SELECT_DELAY_SHORT 50
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#define SELECT_DELAY_LONG 1000
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struct pca9541_plat {
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u32 addr;
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};
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struct pca9541_priv {
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u32 addr;
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unsigned long select_timeout;
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long arb_timeout;
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};
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static inline int mybus(int x)
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{
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return !(x & MYBUS) || ((x & MYBUS) == MYBUS);
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}
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static inline int busoff(int x)
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{
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return !(x & BUSON) || ((x & BUSON) == BUSON);
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}
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static int pca9541_reg_write(struct udevice *mux, struct pca9541_priv *client,
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u8 command, u8 val)
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{
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return dm_i2c_write(mux, command, &val, 1);
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}
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static int pca9541_reg_read(struct udevice *mux, struct pca9541_priv *client,
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u8 command)
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{
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int ret;
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uchar byte;
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ret = dm_i2c_read(mux, command, &byte, 1);
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return ret ?: byte;
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}
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/*
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* Arbitration management functions
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*/
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/* Release bus. Also reset NTESTON and BUSINIT if it was set. */
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static void pca9541_release_bus(struct udevice *mux, struct pca9541_priv *client)
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{
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int reg;
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reg = pca9541_reg_read(mux, client, PCA9541_CONTROL);
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if (reg >= 0 && !busoff(reg) && mybus(reg))
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pca9541_reg_write(mux, client, PCA9541_CONTROL,
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(reg & PCA9541_CTL_NBUSON) >> 1);
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}
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/*
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* Arbitration is defined as a two-step process. A bus master can only activate
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* the slave bus if it owns it; otherwise it has to request ownership first.
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* This multi-step process ensures that access contention is resolved
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* gracefully.
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*
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* Bus Ownership Other master Action
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* state requested access
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* ----------------------------------------------------
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* off - yes wait for arbitration timeout or
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* for other master to drop request
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* off no no take ownership
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* off yes no turn on bus
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* on yes - done
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* on no - wait for arbitration timeout or
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* for other master to release bus
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*
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* The main contention point occurs if the slave bus is off and both masters
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* request ownership at the same time. In this case, one master will turn on
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* the slave bus, believing that it owns it. The other master will request
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* bus ownership. Result is that the bus is turned on, and master which did
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* _not_ own the slave bus before ends up owning it.
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*/
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/* Control commands per PCA9541 datasheet */
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static const u8 pca9541_control[16] = {
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4, 0, 1, 5, 4, 4, 5, 5, 0, 0, 1, 1, 0, 4, 5, 1
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};
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/*
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* Channel arbitration
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*
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* Return values:
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* <0: error
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* 0 : bus not acquired
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* 1 : bus acquired
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*/
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static int pca9541_arbitrate(struct udevice *mux, struct pca9541_priv *client)
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{
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int reg, ret = 0;
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reg = pca9541_reg_read(mux, client, PCA9541_CONTROL);
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if (reg < 0)
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return reg;
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if (busoff(reg)) {
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int istat;
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/*
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* Bus is off. Request ownership or turn it on unless
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* other master requested ownership.
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*/
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istat = pca9541_reg_read(mux, client, PCA9541_ISTAT);
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if (!(istat & PCA9541_ISTAT_NMYTEST) ||
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client->arb_timeout <= 0) {
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/*
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* Other master did not request ownership,
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* or arbitration timeout expired. Take the bus.
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*/
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pca9541_reg_write(mux, client, PCA9541_CONTROL,
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pca9541_control[reg & 0x0f]
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| PCA9541_CTL_NTESTON);
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client->select_timeout = SELECT_DELAY_SHORT;
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} else {
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/*
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* Other master requested ownership.
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* Set extra long timeout to give it time to acquire it.
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*/
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client->select_timeout = SELECT_DELAY_LONG * 2;
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}
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} else if (mybus(reg)) {
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/*
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* Bus is on, and we own it. We are done with acquisition.
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* Reset NTESTON and BUSINIT, then return success.
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*/
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if (reg & (PCA9541_CTL_NTESTON | PCA9541_CTL_BUSINIT))
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pca9541_reg_write(mux, client, PCA9541_CONTROL,
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reg & ~(PCA9541_CTL_NTESTON
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| PCA9541_CTL_BUSINIT));
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ret = 1;
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} else {
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/*
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* Other master owns the bus.
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* If arbitration timeout has expired, force ownership.
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* Otherwise request it.
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*/
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client->select_timeout = SELECT_DELAY_LONG;
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if (client->arb_timeout <= 0) {
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/* Time is up, take the bus and reset it. */
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pca9541_reg_write(mux, client, PCA9541_CONTROL,
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pca9541_control[reg & 0x0f]
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| PCA9541_CTL_BUSINIT
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| PCA9541_CTL_NTESTON);
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} else {
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/* Request bus ownership if needed */
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if (!(reg & PCA9541_CTL_NTESTON))
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pca9541_reg_write(mux, client, PCA9541_CONTROL,
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reg | PCA9541_CTL_NTESTON);
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}
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}
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return ret;
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}
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static int pca9541_select_chan(struct udevice *mux, struct udevice *bus,
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uint channel)
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{
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struct pca9541_priv *priv = dev_get_priv(mux);
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int ret;
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long timeout = ARB2_TIMEOUT_US; /* Give up after this time */
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/* Force bus ownership after this time */
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priv->arb_timeout = ARB_TIMEOUT_US;
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do {
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ret = pca9541_arbitrate(mux, priv);
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if (ret)
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return ret < 0 ? ret : 0;
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udelay(priv->select_timeout);
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timeout -= priv->select_timeout;
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priv->arb_timeout -= priv->select_timeout;
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} while (timeout > 0);
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debug("I2C Arbitration select timeout\n");
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return -ETIMEDOUT;
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}
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static int pca9541_release_chan(struct udevice *mux, struct udevice *bus,
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uint channel)
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{
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struct pca9541_priv *priv = dev_get_priv(mux);
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pca9541_release_bus(mux, priv);
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return 0;
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}
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/*
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* I2C init/probing/exit functions
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*/
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static int pca9541_of_to_plat(struct udevice *dev)
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{
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struct pca9541_plat *plat = dev_get_plat(dev);
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plat->addr = dev_read_u32_default(dev, "reg", 0);
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if (!plat->addr) {
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debug("Reg property is not found\n");
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return -ENODEV;
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}
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debug("Device %s at 0x%x\n", dev->name, plat->addr);
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return 0;
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}
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static int pca9541_probe(struct udevice *dev)
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{
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struct pca9541_plat *plat = dev_get_plat(dev);
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struct pca9541_priv *priv = dev_get_priv(dev);
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priv->addr = plat->addr;
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return 0;
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}
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static const struct i2c_mux_ops pca9541_ops = {
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.select = pca9541_select_chan,
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.deselect = pca9541_release_chan,
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};
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static const struct udevice_id pca9541_ids[] = {
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{ .compatible = "nxp,pca9541", },
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{ }
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};
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U_BOOT_DRIVER(pca9541) = {
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.name = "pca9541",
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.id = UCLASS_I2C_MUX,
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.of_match = pca9541_ids,
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.probe = pca9541_probe,
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.ops = &pca9541_ops,
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.of_to_plat = pca9541_of_to_plat,
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.plat_auto = sizeof(struct pca9541_plat),
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.priv_auto = sizeof(struct pca9541_priv),
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};
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