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d7fb15c17d
Add initial set of clocks and resets for enabling U-Boot on ipq5424 based RDP platforms. Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250304110105.2762124-5-quic_varada@quicinc.com Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
97 lines
2.3 KiB
C
97 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Clock drivers for Qualcomm ipq5424
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*
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* Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <linux/bug.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
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#include <dt-bindings/reset/qcom,ipq5424-gcc.h>
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#include "clock-qcom.h"
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#define GCC_IM_SLEEP_CBCR 0x1834020u
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static ulong ipq5424_set_rate(struct clk *clk, ulong rate)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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switch (clk->id) {
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case GCC_QUPV3_UART1_CLK:
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clk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].reg,
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0, 144, 15625, CFG_CLK_SRC_GPLL0, 16);
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return rate;
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case GCC_SDCC1_APPS_CLK:
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clk_rcg_set_rate_mnd(priv->base, priv->data->clks[clk->id].reg,
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5, 0, 0, CFG_CLK_SRC_GPLL2_MAIN, 16);
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return rate;
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}
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return 0;
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}
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static const struct gate_clk ipq5424_clks[] = {
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GATE_CLK(GCC_QUPV3_UART1_CLK, 0x302c, BIT(0)),
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GATE_CLK(GCC_SDCC1_AHB_CLK, 0x3303c, BIT(0)),
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GATE_CLK(GCC_SDCC1_APPS_CLK, 0x33004, BIT(1)),
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GATE_CLK(GCC_IM_SLEEP_CLK, 0x34020, BIT(0)),
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};
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static int ipq5424_enable(struct clk *clk)
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{
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struct msm_clk_priv *priv = dev_get_priv(clk->dev);
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if (clk->id >= ARRAY_SIZE(ipq5424_clks) || !ipq5424_clks[clk->id].reg)
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return -EINVAL;
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qcom_gate_clk_en(priv, clk->id);
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return 0;
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}
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static const struct qcom_reset_map ipq5424_gcc_resets[] = {
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[GCC_SDCC_BCR] = { 0x33000 },
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};
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static struct msm_clk_data ipq5424_gcc_data = {
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.resets = ipq5424_gcc_resets,
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.num_resets = ARRAY_SIZE(ipq5424_gcc_resets),
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.clks = ipq5424_clks,
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.num_clks = ARRAY_SIZE(ipq5424_clks),
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.enable = ipq5424_enable,
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.set_rate = ipq5424_set_rate,
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};
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static const struct udevice_id gcc_ipq5424_of_match[] = {
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{
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.compatible = "qcom,ipq5424-gcc",
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.data = (ulong)&ipq5424_gcc_data,
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},
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{ }
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};
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static int ipq5424_clk_probe(struct udevice *dev)
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{
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/* Enable the sleep clock needed for the MMC block reset */
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writel(BIT(0), GCC_IM_SLEEP_CBCR);
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return 0;
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}
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U_BOOT_DRIVER(gcc_ipq5424) = {
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.name = "gcc_ipq5424",
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.id = UCLASS_NOP,
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.of_match = gcc_ipq5424_of_match,
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.probe = ipq5424_clk_probe,
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.bind = qcom_cc_bind,
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.flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,
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};
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