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191b10ac70
Migrate the few ARM Layerscape platforms that had not been switched along with all remaining PowerPC platforms to DM_SERIAL. For PowerPC, this means that platforms which use SPL/TPL, keeping the non-DM serial driver enabled there as they do not use DM. We also rework the guards on how to define CFG_SYS_NS16550_CLK so that this is mostly in one place now. Signed-off-by: Tom Rini <trini@konsulko.com>
53 lines
1.2 KiB
C
53 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*/
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#ifndef _ASM_CONFIG_H_
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#define _ASM_CONFIG_H_
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#ifdef CONFIG_MPC85xx
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#include <asm/config_mpc85xx.h>
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#endif
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#ifndef HWCONFIG_BUFFER_SIZE
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#define HWCONFIG_BUFFER_SIZE 256
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#endif
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#ifndef CFG_MAX_MEM_MAPPED
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#if defined(CONFIG_E500) || \
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defined(CONFIG_MPC86xx) || \
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defined(CONFIG_E300)
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#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
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#else
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#define CFG_MAX_MEM_MAPPED (256 << 20)
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#endif
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#endif
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/*
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* Provide a default boot page translation virtual address that lines up with
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* Freescale's default e500 reset page.
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*/
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#if (defined(CONFIG_E500) && defined(CONFIG_MP))
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#define BPTR_VIRT_ADDR 0xfffff000
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#endif
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/* The TSEC driver uses the PHYLIB infrastructure */
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#if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
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#include <config_phylib_all_drivers.h>
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#endif /* TSEC_ENET */
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/* The FMAN driver uses the PHYLIB infrastructure */
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#if !defined(CONFIG_CLK_MPC83XX)
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/*
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* TODO: Convert this to a clock driver exists that can give us the UART
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* clock here.
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*/
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#ifndef CFG_SYS_NS16550_CLK
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#define CFG_SYS_NS16550_CLK get_bus_freq(0)
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#endif
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#endif
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#endif /* _ASM_CONFIG_H_ */
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