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71916a72f1
SPL checks for a magic word in the system manager's scratch register to determine if an L2 reset has occurred. If detected, SPL places all slave CPUs (CPU1–3) into WFI mode. The master CPU (CPU0) then initiates a warm reset by writing to the RMR_EL3 system register and also enters WFI mode. This warm reset flow is handled entirely within the HPS. The function `socfpga_sysreset_request()` triggers the warm reset, and upon SPL re-entry, the updated `lowlevel_init_soc64.S` handles the necessary initialization. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
172 lines
3.9 KiB
ArmAsm
172 lines
3.9 KiB
ArmAsm
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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ENTRY(lowlevel_init)
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mov x29, lr /* Save LR */
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#ifdef CONFIG_XPL_BUILD
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/* Check for L2 reset magic word */
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ldr x4, =L2_RESET_DONE_REG
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ldr x5, [x4]
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ldr x1, =L2_RESET_DONE_STATUS
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cmp x1, x5
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/* No L2 reset, skip warm reset */
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b.ne skipwarmreset
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/* Put all slaves CPUs into WFI mode */
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branch_if_slave x0, put_cpu_in_wfi
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/* L2 reset completed */
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str xzr, [x4]
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/* Clear previous CPU release address */
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ldr x4, =CPU_RELEASE_ADDR
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str wzr, [x4]
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/* Master CPU (CPU0) request for warm reset */
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mrs x1, rmr_el3
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orr x1, x1, #0x02
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msr rmr_el3, x1
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isb
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dsb sy
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put_cpu_in_wfi:
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wfi
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b put_cpu_in_wfi
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skipwarmreset:
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#endif
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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#if defined(CONFIG_XPL_BUILD) && defined(CONFIG_SPL_ATF)
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/*
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* In ATF flow, need to clear the old CPU address when cold reset
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* being triggered, but shouldn't clear CPU address if it is reset
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* by CPU-ON, so that the core can correctly jump to ATF code after
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* reset by CPU-ON. CPU-ON trigger the reset via mpumodrst.
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*
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* Hardware will set 1 to core*_irq in mpurststat register in
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* reset manager if the core is reset by mpumodrst.
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*
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* The following code will check the mpurststat to identify if the
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* core is reset by mpumodrst, and it will skip CPU address clearing
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* if the core is reset by mpumodrst. At last, the code need to clear
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* the core*_irq by set it to 1. So that it can reflect the correct
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* and latest status in next reset.
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*/
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/* Check if it is a master core off/on from kernel using boot scratch
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* cold register 8 bit 19. This bit is set by ATF.
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*/
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ldr x4, =BOOT_SCRATCH_COLD8
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ldr x5, [x4]
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and x6, x5, #0x80000
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cbnz x6, wait_for_atf_master
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/* Retrieve mpurststat register in reset manager */
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ldr x4, =SOCFPGA_RSTMGR_ADDRESS
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ldr w5, [x4, #0x04]
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/* Set mask based on current core id */
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mrs x0, mpidr_el1
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and x1, x0, #0xF
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ldr x2, =0x00000100
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lsl x2, x2, x1
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/* Skip if core*_irq register is set */
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and x6, x5, x2
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cbnz x6, skip_clear_cpu_address
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/*
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* Reach here means core*_irq is 0, means the core is
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* reset by cold, warm or watchdog reset.
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* Clear previous CPU release address
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*/
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ldr x4, =CPU_RELEASE_ADDR
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str wzr, [x4]
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b skip_clear_core_irq
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skip_clear_cpu_address:
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/* Clear core*_irq register by writing 1 */
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ldr x4, =SOCFPGA_RSTMGR_ADDRESS
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str w2, [x4, #0x04]
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skip_clear_core_irq:
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/* Master CPU (CPU0) does not need to wait for atf */
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branch_if_master x0, master_cpu
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wait_for_atf:
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ldr x4, =CPU_RELEASE_ADDR
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ldr x5, [x4]
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cbz x5, slave_wait_atf
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br x5
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slave_wait_atf:
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branch_if_slave x0, wait_for_atf
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wait_for_atf_master:
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ldr x4, =CPU_RELEASE_ADDR
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ldr x5, [x4]
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cbz x5, master_wait_atf
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br x5
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master_wait_atf:
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branch_if_master x0, wait_for_atf_master
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master_cpu:
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#else
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branch_if_slave x0, 1f
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#endif
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ldr x0, =GICD_BASE
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bl gic_init_secure
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1:
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#if defined(CONFIG_GICV3)
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ldr x0, =GICR_BASE
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bl gic_init_secure_percpu
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#elif defined(CONFIG_GICV2)
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ldr x0, =GICD_BASE
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ldr x1, =GICC_BASE
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bl gic_init_secure_percpu
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#endif
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#endif
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#ifdef CONFIG_ARMV8_MULTIENTRY
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branch_if_master x0, 2f
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/*
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* Slave should wait for master clearing spin table.
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* This sync prevent slaves observing incorrect
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* value of spin table and jumping to wrong place.
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*/
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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#ifdef CONFIG_GICV2
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ldr x0, =GICC_BASE
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#endif
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bl gic_wait_for_interrupt
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#endif
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/*
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* All slaves will enter EL2 and optionally EL1.
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*/
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adr x4, lowlevel_in_el2
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ldr x5, =ES_TO_AARCH64
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bl armv8_switch_to_el2
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lowlevel_in_el2:
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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adr x4, lowlevel_in_el1
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ldr x5, =ES_TO_AARCH64
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bl armv8_switch_to_el1
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lowlevel_in_el1:
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#endif
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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2:
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mov lr, x29 /* Restore LR */
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ret
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ENDPROC(lowlevel_init)
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