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Naresh Kumar Ravulapalli da57acb4c3 arch: arm: socfpga: Configure USB3 System Manager registers 
For successful reset staggering pulse operation, reset pulse
override bit is set. Port overcurrent bit 1, which in reality
reflects PIPE power present signal is set to avoid giving
false information of Vbus status to HPS controller.

Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
2025-09-30 14:45:37 +08:00
..
mach
arch: arm: socfpga: Configure USB3 System Manager registers
2025-09-30 14:45:37 +08:00