mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-12-23 10:21:28 +01:00
b82a1fa7dd
-----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTzzqh0PWDgGS+bTHor4qD1Cr/kCgUCaNKh1AAKCRAr4qD1Cr/k CnQgAQD5TlXCGlBUqvpBo8Q4eoWQb+bIjP7UJlquO3nB9vrqAgD/cpKwXDBZ88fL 7UwAs2FAuE21eJ/SwZ/NQImwR0CkNAk= =N0hy -----END PGP SIGNATURE----- Merge tag 'v2025.10-rc5' into next Prepare v2025.10-rc5
237 lines
3.6 KiB
Plaintext
237 lines
3.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2025 NXP
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*/
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/ {
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binman {
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multiple-images;
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m33-oei-ddrfw {
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pad-byte = <0x00>;
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align-size = <0x8>;
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filename = "m33-oei-ddrfw.bin";
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oei-m33-ddr {
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align-size = <0x4>;
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filename = "oei-m33-ddr.bin";
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type = "blob-ext";
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};
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imx-lpddr {
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type = "nxp-header-ddrfw";
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imx-lpddr-imem {
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filename = "lpddr5_imem_v202409.bin";
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type = "blob-ext";
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};
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imx-lpddr-dmem {
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filename = "lpddr5_dmem_v202409.bin";
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type = "blob-ext";
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};
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};
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imx-lpddr-qb {
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type = "nxp-header-ddrfw";
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imx-lpddr-imem-qb {
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filename = "lpddr5_imem_qb_v202409.bin";
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type = "blob-ext";
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};
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imx-lpddr-dmem-qb {
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filename = "lpddr5_dmem_qb_v202409.bin";
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type = "blob-ext";
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};
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};
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};
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imx-boot {
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filename = "flash.bin";
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pad-byte = <0x00>;
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spl {
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type = "nxp-imx9image";
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cfg-path = "spl/u-boot-spl.cfgout";
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args;
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#ifndef CONFIG_IMX95_A0
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cntr-version = <2>;
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#endif
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boot-from = "sd";
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soc-type = "IMX9";
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#ifdef CONFIG_IMX95_A0
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append = "mx95a0-ahab-container.img";
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#else
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append = "mx95b0-ahab-container.img";
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#endif
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container;
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#ifndef CONFIG_IMX95_A0
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dummy-ddr;
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#endif
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image0 = "oei", "m33-oei-ddrfw.bin", "0x1ffc0000";
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hold = <0x10000>;
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#ifdef CONFIG_IMX95_A0
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image1 = "oei", "oei-m33-tcm.bin", "0x1ffc0000";
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#endif
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image2 = "m33", "m33_image.bin", "0x1ffc0000";
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image3 = "a55", "spl/u-boot-spl.bin", "0x20480000";
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dummy-v2x = <0x8b000000>;
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};
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u-boot {
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type = "nxp-imx9image";
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cfg-path = "u-boot-container.cfgout";
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args;
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#ifndef CONFIG_IMX95_A0
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cntr-version = <2>;
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#endif
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boot-from = "sd";
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soc-type = "IMX9";
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container;
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image0 = "a55", "bl31.bin", "0x8a200000";
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image1 = "a55", "u-boot.bin", "0x90200000";
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};
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};
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};
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};
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&A55_0 {
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clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
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/delete-property/ power-domains;
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};
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&A55_1 {
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clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
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/delete-property/ power-domains;
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};
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&A55_2 {
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clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
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/delete-property/ power-domains;
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};
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&A55_3 {
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clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
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/delete-property/ power-domains;
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};
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&A55_4 {
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clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
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/delete-property/ power-domains;
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};
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&A55_5 {
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clocks = <&scmi_clk IMX95_CLK_ARMPLL_PFD0>;
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/delete-property/ power-domains;
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};
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&aips1 {
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bootph-all;
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};
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&aips2 {
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bootph-all;
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};
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&aips3 {
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bootph-pre-ram;
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};
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&clk_ext1 {
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bootph-all;
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};
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&elemu1 {
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bootph-all;
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status = "okay";
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};
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&elemu3 {
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bootph-all;
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status = "okay";
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};
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&{/firmware} {
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bootph-all;
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};
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&{/firmware/scmi} {
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bootph-all;
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};
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&{/firmware/scmi/protocol@11} {
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bootph-all;
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};
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&{/firmware/scmi/protocol@13} {
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bootph-all;
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};
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&{/firmware/scmi/protocol@14} {
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bootph-all;
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};
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&{/firmware/scmi/protocol@19} {
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bootph-all;
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};
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&gpio2 {
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bootph-pre-ram;
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};
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&gpio3 {
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bootph-pre-ram;
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};
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&gpio4 {
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bootph-pre-ram;
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};
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&gpio5 {
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bootph-pre-ram;
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};
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&mu2 {
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bootph-all;
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};
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&osc_24m {
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bootph-all;
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};
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&pcie0 {
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assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
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<&scmi_clk IMX95_CLK_HSIOPLL>,
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<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
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assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
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<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
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};
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&pcie1 {
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assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
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<&scmi_clk IMX95_CLK_HSIOPLL>,
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<&scmi_clk IMX95_CLK_HSIOPCIEAUX>;
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assigned-clock-parents = <0>, <&scmi_clk IMX95_CLK_HSIOPLL_VCO>,
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<&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>;
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};
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&{/soc} {
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bootph-all;
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};
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&sram0 {
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bootph-all;
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};
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&scmi_buf0 {
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reg = <0x0 0x400>;
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bootph-all;
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};
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&scmi_buf1 {
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bootph-all;
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};
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