mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-12-24 10:52:13 +01:00
b40c9b0c22
Add the initial board support for the NXP i.MX93 FRDM board: https://www.nxp.com/design/design-center/development-boards-and-designs/frdm-i-mx-93-development-board:FRDM-IMX93 Based on the NXP U-Boot code. There were attempts to upstream the board devicetree, but it has not been accepted upstream yet: https://lore.kernel.org/linux-arm-kernel/20250526-fpg-nxp-imx93-frdm-v2-2-e5ad0efaec33@pengutronix.de/ Once it reaches upstream, we can switch to OF_UPSTREAM. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
604 lines
15 KiB
Plaintext
604 lines
15 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/dts-v1/;
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#include <dt-bindings/usb/pd.h>
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#include "imx93.dtsi"
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/ {
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compatible = "fsl,imx93-11x11-frdm", "fsl,imx93";
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model = "NXP i.MX93 11X11 FRDM board";
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aliases {
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mmc0 = &usdhc1; /* EMMC */
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mmc1 = &usdhc2; /* uSD */
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rtc0 = &pcf2131;
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serial0 = &lpuart1;
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};
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chosen {
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stdout-path = &lpuart1;
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};
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reg_vref_1v8: regulator-adc-vref {
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compatible = "regulator-fixed";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vref_1v8";
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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off-on-delay-us = <12000>;
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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pinctrl-names = "default";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "VSD_3V3";
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gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_usdhc3_vmmc: regulator-usdhc3 {
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compatible = "regulator-fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "WLAN_EN";
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gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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/*
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* IW612 wifi chip needs more delay than other wifi chips to complete
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* the host interface initialization after power up, otherwise the
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* internal state of IW612 may be unstable, resulting in the failure of
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* the SDIO3.0 switch voltage.
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*/
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startup-delay-us = <20000>;
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};
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reserved-memory {
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ranges;
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#address-cells = <2>;
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#size-cells = <2>;
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linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0 0x80000000 0 0x30000000>;
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reusable;
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size = <0 0x10000000>;
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linux,cma-default;
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};
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rsc_table: rsc-table@2021e000 {
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reg = <0 0x2021e000 0 0x1000>;
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no-map;
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};
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vdev0vring0: vdev0vring0@a4000000 {
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reg = <0 0xa4000000 0 0x8000>;
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no-map;
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};
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vdev0vring1: vdev0vring1@a4008000 {
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reg = <0 0xa4008000 0 0x8000>;
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no-map;
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};
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vdev1vring0: vdev1vring0@a4010000 {
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reg = <0 0xa4010000 0 0x8000>;
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no-map;
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};
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vdev1vring1: vdev1vring1@a4018000 {
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reg = <0 0xa4018000 0 0x8000>;
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no-map;
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};
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vdevbuffer: vdevbuffer@a4020000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa4020000 0 0x100000>;
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no-map;
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};
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};
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usdhc3_pwrseq: usdhc3_pwrseq {
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compatible = "mmc-pwrseq-simple";
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reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>;
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};
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};
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&adc1 {
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vref-supply = <®_vref_1v8>;
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status = "okay";
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};
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&eqos {
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phy-handle = <ðphy1>;
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phy-mode = "rgmii-id";
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pinctrl-0 = <&pinctrl_eqos>;
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pinctrl-1 = <&pinctrl_eqos_sleep>;
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pinctrl-names = "default", "sleep";
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <5000000>;
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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reset-assert-us = <10000>;
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reset-deassert-us = <80000>;
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reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&fec {
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phy-handle = <ðphy2>;
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phy-mode = "rgmii-id";
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pinctrl-0 = <&pinctrl_fec>;
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pinctrl-1 = <&pinctrl_fec_sleep>;
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pinctrl-names = "default", "sleep";
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <5000000>;
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ethphy2: ethernet-phy@2 {
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reg = <2>;
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eee-broken-1000t;
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reset-assert-us = <10000>;
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reset-deassert-us = <80000>;
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reset-gpios = <&pcal6524 16 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&lpi2c2 {
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clock-frequency = <400000>;
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pinctrl-0 = <&pinctrl_lpi2c2>;
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pinctrl-names = "default";
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status = "okay";
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pcal6524: gpio@22 {
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compatible = "nxp,pcal6524";
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reg = <0x22>;
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#interrupt-cells = <2>;
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interrupt-controller;
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interrupt-parent = <&gpio3>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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#gpio-cells = <2>;
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gpio-controller;
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pinctrl-0 = <&pinctrl_pcal6524>;
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pinctrl-names = "default";
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};
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pmic@25 {
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compatible = "nxp,pca9451a";
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reg = <0x25>;
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interrupt-parent = <&pcal6524>;
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interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
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regulators {
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buck1: BUCK1 {
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regulator-name = "BUCK1";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <650000>;
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regulator-max-microvolt = <2237500>;
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regulator-ramp-delay = <3125>;
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};
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buck2: BUCK2 {
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regulator-name = "BUCK2";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-ramp-delay = <3125>;
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};
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buck4: BUCK4 {
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regulator-name = "BUCK4";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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};
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buck5: BUCK5 {
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regulator-name = "BUCK5";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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};
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buck6: BUCK6 {
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regulator-name = "BUCK6";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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};
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ldo1: LDO1 {
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regulator-name = "LDO1";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <3300000>;
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};
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ldo4: LDO4 {
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regulator-name = "LDO4";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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};
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ldo5: LDO5 {
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regulator-name = "LDO5";
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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eeprom: eeprom@50 {
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compatible = "atmel,24c256";
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reg = <0x50>;
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pagesize = <64>;
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};
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};
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&lpi2c3 {
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <400000>;
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pinctrl-0 = <&pinctrl_lpi2c3>;
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pinctrl-names = "default";
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status = "okay";
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ptn5110: tcpc@50 {
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compatible = "nxp,ptn5110", "tcpci";
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reg = <0x50>;
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interrupt-parent = <&gpio3>;
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interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
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typec1_con: connector {
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compatible = "usb-c-connector";
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data-role = "dual";
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label = "USB-C";
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op-sink-microwatt = <15000000>;
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power-role = "dual";
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self-powered;
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sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
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PDO_VAR(5000, 20000, 3000)>;
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source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
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try-power-role = "sink";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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typec1_dr_sw: endpoint {
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remote-endpoint = <&usb1_drd_sw>;
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};
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};
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};
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};
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};
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pcf2131: rtc@53 {
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compatible = "nxp,pcf2131";
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reg = <0x53>;
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interrupt-parent = <&pcal6524>;
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interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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&lpuart1 { /* console */
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pinctrl-0 = <&pinctrl_uart1>;
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pinctrl-names = "default";
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status = "okay";
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};
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&usbotg1 {
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adp-disable;
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disable-over-current;
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dr_mode = "otg";
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hnp-disable;
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srp-disable;
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usb-role-switch;
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samsung,picophy-dc-vol-level-adjust = <7>;
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samsung,picophy-pre-emp-curr-control = <3>;
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status = "okay";
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port {
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usb1_drd_sw: endpoint {
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remote-endpoint = <&typec1_dr_sw>;
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};
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};
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};
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&usbotg2 {
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disable-over-current;
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dr_mode = "host";
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samsung,picophy-dc-vol-level-adjust = <7>;
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samsung,picophy-pre-emp-curr-control = <3>;
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status = "okay";
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};
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&usdhc1 {
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bus-width = <8>;
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non-removable;
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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status = "okay";
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};
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&usdhc2 {
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bus-width = <4>;
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cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
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no-mmc;
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no-sdio;
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&wdog3 {
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status = "okay";
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};
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&iomuxc {
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
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MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
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MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
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MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
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MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
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MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
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MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
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MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
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MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
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MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
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MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
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MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
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MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
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MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
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>;
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};
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pinctrl_eqos_sleep: eqossleepgrp {
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fsl,pins = <
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MX93_PAD_ENET1_MDC__GPIO4_IO00 0x31e
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MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x31e
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MX93_PAD_ENET1_RD0__GPIO4_IO10 0x31e
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MX93_PAD_ENET1_RD1__GPIO4_IO11 0x31e
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MX93_PAD_ENET1_RD2__GPIO4_IO12 0x31e
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MX93_PAD_ENET1_RD3__GPIO4_IO13 0x31e
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MX93_PAD_ENET1_RXC__GPIO4_IO09 0x31e
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MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x31e
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MX93_PAD_ENET1_TD0__GPIO4_IO05 0x31e
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MX93_PAD_ENET1_TD1__GPIO4_IO04 0x31e
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MX93_PAD_ENET1_TD2__GPIO4_IO03 0x31e
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MX93_PAD_ENET1_TD3__GPIO4_IO02 0x31e
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MX93_PAD_ENET1_TXC__GPIO4_IO07 0x31e
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MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x31e
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX93_PAD_ENET2_MDC__ENET1_MDC 0x57e
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MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x57e
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MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e
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MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e
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MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e
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MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e
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MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x58e
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MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e
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MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x57e
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MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x57e
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MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x57e
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MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x57e
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MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e
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MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x57e
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>;
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};
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pinctrl_fec_sleep: fecsleepgrp {
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fsl,pins = <
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MX93_PAD_ENET2_MDC__GPIO4_IO14 0x51e
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MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x51e
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MX93_PAD_ENET2_RD0__GPIO4_IO24 0x51e
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MX93_PAD_ENET2_RD1__GPIO4_IO25 0x51e
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MX93_PAD_ENET2_RD2__GPIO4_IO26 0x51e
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MX93_PAD_ENET2_RD3__GPIO4_IO27 0x51e
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MX93_PAD_ENET2_RXC__GPIO4_IO23 0x51e
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MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e
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MX93_PAD_ENET2_TD0__GPIO4_IO19 0x51e
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MX93_PAD_ENET2_TD1__GPIO4_IO18 0x51e
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MX93_PAD_ENET2_TD2__GPIO4_IO17 0x51e
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MX93_PAD_ENET2_TD3__GPIO4_IO16 0x51e
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MX93_PAD_ENET2_TXC__GPIO4_IO21 0x51e
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MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
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>;
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};
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pinctrl_flexcan2: flexcan2grp {
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fsl,pins = <
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MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
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MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
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>;
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};
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pinctrl_lpi2c2: lpi2c2grp {
|
|
fsl,pins = <
|
|
MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
|
|
MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
|
|
>;
|
|
};
|
|
|
|
pinctrl_lpi2c3: lpi2c3grp {
|
|
fsl,pins = <
|
|
MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e
|
|
MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e
|
|
>;
|
|
};
|
|
|
|
pinctrl_pcal6524: pcal6524grp {
|
|
fsl,pins = <
|
|
MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
|
|
MX93_PAD_UART1_TXD__LPUART1_TX 0x31e
|
|
>;
|
|
};
|
|
|
|
/* need to config the SION for data and cmd pad, refer to ERR052021 */
|
|
pinctrl_usdhc1: usdhc1grp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582
|
|
MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382
|
|
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382
|
|
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382
|
|
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382
|
|
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382
|
|
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382
|
|
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382
|
|
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382
|
|
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382
|
|
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
|
|
>;
|
|
};
|
|
|
|
/* need to config the SION for data and cmd pad, refer to ERR052021 */
|
|
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e
|
|
MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e
|
|
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e
|
|
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e
|
|
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e
|
|
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e
|
|
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e
|
|
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e
|
|
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e
|
|
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e
|
|
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
|
|
>;
|
|
};
|
|
|
|
/* need to config the SION for data and cmd pad, refer to ERR052021 */
|
|
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
|
|
MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe
|
|
MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe
|
|
MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe
|
|
MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe
|
|
MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe
|
|
MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe
|
|
MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe
|
|
MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe
|
|
MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe
|
|
MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x51e
|
|
>;
|
|
};
|
|
|
|
/* need to config the SION for data and cmd pad, refer to ERR052021 */
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582
|
|
MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382
|
|
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382
|
|
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382
|
|
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382
|
|
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382
|
|
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
|
|
>;
|
|
};
|
|
|
|
/* need to config the SION for data and cmd pad, refer to ERR052021 */
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e
|
|
MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e
|
|
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e
|
|
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e
|
|
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e
|
|
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e
|
|
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
|
|
>;
|
|
};
|
|
|
|
/* need to config the SION for data and cmd pad, refer to ERR052021 */
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe
|
|
MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe
|
|
MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe
|
|
MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe
|
|
MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe
|
|
MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe
|
|
MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
|
|
fsl,pins = <
|
|
MX93_PAD_SD2_CLK__GPIO3_IO01 0x51e
|
|
MX93_PAD_SD2_CMD__GPIO3_IO02 0x51e
|
|
MX93_PAD_SD2_DATA0__GPIO3_IO03 0x51e
|
|
MX93_PAD_SD2_DATA1__GPIO3_IO04 0x51e
|
|
MX93_PAD_SD2_DATA2__GPIO3_IO05 0x51e
|
|
MX93_PAD_SD2_DATA3__GPIO3_IO06 0x51e
|
|
MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x51e
|
|
>;
|
|
};
|
|
};
|