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a3ab2ae7f6
Update definitions for processor, registers as well as assemby macros. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
139 lines
3.4 KiB
C
139 lines
3.4 KiB
C
/*
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* Copyright (C) 1994 Waldorf GMBH
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* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
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* Copyright (C) 1996 Paul M. Antoine
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_PROCESSOR_H
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#define _ASM_PROCESSOR_H
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#include <asm/isadep.h>
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#include <asm/cachectl.h>
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#include <asm/mipsregs.h>
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#include <asm/reg.h>
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#include <asm/system.h>
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/*
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* Return current * instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ __label__ _l; _l: &&_l;})
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/*
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* System setup and hardware flags..
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*/
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extern void (*cpu_wait)(void);
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extern unsigned int vced_count, vcei_count;
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#define NUM_FPU_REGS 32
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typedef __u64 fpureg_t;
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/*
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* It would be nice to add some more fields for emulator statistics, but there
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* are a number of fixed offsets in offset.h and elsewhere that would have to
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* be recalculated by hand. So the additional information will be private to
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* the FPU emulator for now. See asm-mips/fpu_emulator.h.
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*/
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struct mips_fpu_struct {
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fpureg_t fpr[NUM_FPU_REGS];
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unsigned int fcr31;
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};
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#define NUM_DSP_REGS 6
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typedef __u32 dspreg_t;
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struct mips_dsp_state {
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dspreg_t dspr[NUM_DSP_REGS];
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unsigned int dspcontrol;
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};
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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#define ARCH_MIN_TASKALIGN 8
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struct mips_abi;
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/*
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* If you change thread_struct remember to change the #defines below too!
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*/
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struct thread_struct {
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/* Saved main processor registers. */
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unsigned long reg16;
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unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
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unsigned long reg29, reg30, reg31;
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/* Saved cp0 stuff. */
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unsigned long cp0_status;
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/* Saved fpu/fpu emulator stuff. */
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struct mips_fpu_struct fpu;
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#ifdef CONFIG_MIPS_MT_FPAFF
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/* Emulated instruction count */
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unsigned long emulated_fp;
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/* Saved per-thread scheduler affinity mask */
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cpumask_t user_cpus_allowed;
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#endif /* CONFIG_MIPS_MT_FPAFF */
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/* Saved state of the DSP ASE, if available. */
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struct mips_dsp_state dsp;
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/* Other stuff associated with the thread. */
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unsigned long cp0_badvaddr; /* Last user fault */
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unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
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unsigned long error_code;
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unsigned long trap_no;
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unsigned long irix_trampoline; /* Wheee... */
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unsigned long irix_oldctx;
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struct mips_abi *abi;
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};
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struct task_struct;
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/* Free all resources held by a thread. */
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#define release_thread(thread) do { } while(0)
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/* Prepare to copy thread state - unlazy all lazy status */
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#define prepare_to_copy(tsk) do { } while (0)
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#define cpu_relax() barrier()
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/*
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* Return_address is a replacement for __builtin_return_address(count)
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* which on certain architectures cannot reasonably be implemented in GCC
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* (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
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* Note that __builtin_return_address(x>=1) is forbidden because GCC
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* aborts compilation on some CPUs. It's simply not possible to unwind
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* some CPU's stackframes.
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*
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* __builtin_return_address works only for non-leaf functions. We avoid the
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* overhead of a function call by forcing the compiler to save the return
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* address register on the stack.
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*/
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#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
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#ifdef CONFIG_CPU_HAS_PREFETCH
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#define ARCH_HAS_PREFETCH
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static inline void prefetch(const void *addr)
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{
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__asm__ __volatile__(
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" .set mips4 \n"
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" pref %0, (%1) \n"
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" .set mips0 \n"
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:
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: "i" (Pref_Load), "r" (addr));
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}
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#endif
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#endif /* _ASM_PROCESSOR_H */
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