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			68 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			68 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
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|  *
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|  * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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|  * Copyright (C) 2007 Andrew Victor
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|  * Copyright (C) 2007 Atmel Corporation.
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|  *
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|  * Watchdog Timer (WDT) - System peripherals regsters.
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|  * Based on AT91SAM9261 datasheet revision D.
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|  *
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|  * This program is free software; you can redistribute it and/or modify
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|  * it under the terms of the GNU General Public License as published by
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|  * the Free Software Foundation; either version 2 of the License, or
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|  * (at your option) any later version.
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|  */
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| 
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| #ifndef AT91_WDT_H
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| #define AT91_WDT_H
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| 
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| #ifdef __ASSEMBLY__
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| 
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| #define AT91_ASM_WDT_MR	(ATMEL_BASE_WDT +  0x04)
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| 
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| #else
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| 
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| typedef struct at91_wdt {
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| 	u32	cr;
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| 	u32	mr;
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| 	u32	sr;
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| } at91_wdt_t;
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| 
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| #endif
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| 
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| #define AT91_WDT_CR_WDRSTT		1
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| #define AT91_WDT_CR_KEY			0xa5000000	/* KEY Password */
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| 
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| #define AT91_WDT_MR_WDV(x)		(x & 0xfff)
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| #define AT91_WDT_MR_WDFIEN		0x00001000
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| #define AT91_WDT_MR_WDRSTEN		0x00002000
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| #define AT91_WDT_MR_WDRPROC		0x00004000
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| #define AT91_WDT_MR_WDDIS		0x00008000
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| #define AT91_WDT_MR_WDD(x)		((x & 0xfff) << 16)
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| #define AT91_WDT_MR_WDDBGHLT		0x10000000
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| #define AT91_WDT_MR_WDIDLEHLT		0x20000000
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| 
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| #ifdef CONFIG_AT91_LEGACY
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| 
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| #define AT91_WDT_CR		(AT91_WDT + 0x00)	/* Watchdog Control Register */
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| #define		AT91_WDT_WDRSTT		(1    << 0)		/* Restart */
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| #define		AT91_WDT_KEY		(0xa5 << 24)		/* KEY Password */
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| 
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| #define AT91_WDT_MR		(AT91_WDT + 0x04)	/* Watchdog Mode Register */
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| #define		AT91_WDT_WDV		(0xfff << 0)		/* Counter Value */
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| #define		AT91_WDT_WDFIEN		(1     << 12)		/* Fault Interrupt Enable */
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| #define		AT91_WDT_WDRSTEN	(1     << 13)		/* Reset Processor */
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| #define		AT91_WDT_WDRPROC	(1     << 14)		/* Timer Restart */
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| #define		AT91_WDT_WDDIS		(1     << 15)		/* Watchdog Disable */
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| #define		AT91_WDT_WDD		(0xfff << 16)		/* Delta Value */
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| #define		AT91_WDT_WDDBGHLT	(1     << 28)		/* Debug Halt */
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| #define		AT91_WDT_WDIDLEHLT	(1     << 29)		/* Idle Halt */
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| 
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| #define AT91_WDT_SR		(AT91_WDT + 0x08)	/* Watchdog Status Register */
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| #define		AT91_WDT_WDUNF		(1 << 0)		/* Watchdog Underflow */
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| #define		AT91_WDT_WDERR		(1 << 1)		/* Watchdog Error */
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| 
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| #endif /* CONFIG_AT91_LEGACY */
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| #endif
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