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35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
96 lines
2.0 KiB
C
96 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <log.h>
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#include <asm/global_data.h>
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#include <linux/arm-smccc.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/pmc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
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static bool tegra_pmc_detect_tz_only(void)
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{
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static bool initialized = false;
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static bool is_tz_only = false;
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u32 value, saved;
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if (!initialized) {
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saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
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value = saved ^ 0xffffffff;
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if (value == 0xffffffff)
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value = 0xdeadbeef;
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/* write pattern and read it back */
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writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0);
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value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
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/* if we read all-zeroes, access is restricted to TZ only */
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if (value == 0) {
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debug("access to PMC is restricted to TZ\n");
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is_tz_only = true;
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} else {
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/* restore original value */
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writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0);
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}
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initialized = true;
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}
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return is_tz_only;
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}
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#endif
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uint32_t tegra_pmc_readl(unsigned long offset)
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{
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#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
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if (tegra_pmc_detect_tz_only()) {
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struct arm_smccc_res res;
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arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
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0, 0, 0, &res);
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if (res.a0)
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printf("%s(): SMC failed: %lu\n", __func__, res.a0);
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return res.a1;
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}
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#endif
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return readl(NV_PA_PMC_BASE + offset);
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}
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void tegra_pmc_writel(u32 value, unsigned long offset)
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{
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#if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
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if (tegra_pmc_detect_tz_only()) {
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struct arm_smccc_res res;
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arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
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value, 0, 0, 0, 0, &res);
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if (res.a0)
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printf("%s(): SMC failed: %lu\n", __func__, res.a0);
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return;
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}
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#endif
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writel(value, NV_PA_PMC_BASE + offset);
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}
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void reset_cpu(void)
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{
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u32 value;
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value = tegra_pmc_readl(PMC_CNTRL);
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value |= PMC_CNTRL_MAIN_RST;
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tegra_pmc_writel(value, PMC_CNTRL);
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}
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