Kever Yang 5793e8c271 rockchip: clk: rk322x: fix assert clock value
BUS_PCLK_HZ and BUS_HCLK_HZ are from BUS_ACLK_HZ, not from GPLL_HZ.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2019-05-08 17:34:12 +08:00
..
2019-04-25 17:03:25 +02:00
2019-04-23 11:19:09 +02:00
2018-08-03 19:53:10 -04:00
2018-05-08 18:50:23 -04:00
2018-09-18 00:01:18 -06:00
2018-09-18 00:01:18 -06:00