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d508d995d1
Add a clock driver for the PRCM clock controller on the Allwinner A523 family of SoCs, often also used with an "r" prefix or suffix. This just describes the clock gates and reset lines for the few devices that we would need, most prominently the R_I2C device for the PMIC. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
40 lines
1.2 KiB
C
40 lines
1.2 KiB
C
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2024 Arm Ltd.
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*/
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#include <clk-uclass.h>
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#include <dm.h>
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#include <clk/sunxi.h>
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#include <dt-bindings/clock/sun55i-a523-r-ccu.h>
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#include <dt-bindings/reset/sun55i-a523-r-ccu.h>
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#include <linux/bitops.h>
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static struct ccu_clk_gate a523_r_gates[] = {
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[CLK_R_AHB] = GATE_DUMMY,
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[CLK_R_APB0] = GATE_DUMMY,
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[CLK_R_APB1] = GATE_DUMMY,
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[CLK_BUS_R_TWD] = GATE(0x12c, BIT(0)),
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[CLK_BUS_R_I2C0] = GATE(0x19c, BIT(0)),
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[CLK_BUS_R_I2C1] = GATE(0x19c, BIT(1)),
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[CLK_BUS_R_I2C2] = GATE(0x19c, BIT(2)),
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[CLK_BUS_R_RTC] = GATE(0x20c, BIT(0)),
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};
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static struct ccu_reset a523_r_resets[] = {
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[RST_BUS_R_TWD] = RESET(0x12c, BIT(16)),
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[RST_BUS_R_UART0] = RESET(0x18c, BIT(16)),
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[RST_BUS_R_I2C0] = RESET(0x19c, BIT(16)),
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[RST_BUS_R_I2C1] = RESET(0x19c, BIT(17)),
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[RST_BUS_R_I2C2] = RESET(0x19c, BIT(18)),
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[RST_BUS_R_PPU1] = RESET(0x1ac, BIT(17)),
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[RST_BUS_R_RTC] = RESET(0x20c, BIT(16)),
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};
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const struct ccu_desc a523_r_ccu_desc = {
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.gates = a523_r_gates,
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.resets = a523_r_resets,
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.num_gates = ARRAY_SIZE(a523_r_gates),
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.num_resets = ARRAY_SIZE(a523_r_resets),
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};
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