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da57acb4c3
For successful reset staggering pulse operation, reset pulse override bit is set. Port overcurrent bit 1, which in reality reflects PIPE power present signal is set to avoid giving false information of Vbus status to HPS controller. Signed-off-by: Naresh Kumar Ravulapalli <nareshkumar.ravulapalli@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
143 lines
4.6 KiB
C
143 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
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*
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*/
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#include <asm/arch/handoff_soc64.h>
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#include <asm/arch/system_manager.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/bitfield.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
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/*
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* Setting RESET_PULSE_OVERRIDE bit for successful reset staggering pulse
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* generation and setting PORT_OVERCURRENT bit so that until we turn on the
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* Vbus, it doesn't give false information about Vbus to the HPS controller.
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*/
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static void sysmgr_config_usb3(void)
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{
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u32 reg_val = 0;
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reg_val = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0);
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reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_RESET_PUL_OVR,
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SET_USB3_MISC_CTRL_REG0_PORT_RESET_PUL_OVR);
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reg_val |= FIELD_PREP(SYSMGR_SOC64_USB3_MISC_CTRL_REG0_PORT_OVR_CURR,
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SET_USB3_MISC_CTRL_REG0_PORT_OVR_CURR_BIT_1);
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writel(reg_val, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_USB3_MISC_CTRL_REG0);
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}
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#endif
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/*
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* Configure all the pin muxes
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*/
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void sysmgr_pinmux_init(void)
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{
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populate_sysmgr_pinmux();
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populate_sysmgr_fpgaintf_module();
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
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sysmgr_config_usb3();
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#endif
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}
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/*
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* Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
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* The value is not wrote to SYSMGR.FPGAINTF.MODULE but
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* CONFIG_SYSMGR_ISWGRP_HANDOFF.
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*/
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void populate_sysmgr_fpgaintf_module(void)
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{
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u32 handoff_val = 0;
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/* Enable the signal for those HPS peripherals that use FPGA. */
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NAND_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_NAND;
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SDMMC_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_SDMMC;
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM0_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_SPIM0;
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_SPIM1_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_SPIM1;
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writel(handoff_val,
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socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN2);
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handoff_val = 0;
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC0_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_EMAC0;
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC1_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_EMAC1;
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if (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_EMAC2_USEFPGA) ==
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SYSMGR_FPGAINTF_USEFPGA)
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handoff_val |= SYSMGR_FPGAINTF_EMAC2;
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writel(handoff_val,
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socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGAINTF_EN3);
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}
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/*
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* Configure all the pin muxes
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*/
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void populate_sysmgr_pinmux(void)
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{
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u32 len, i;
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u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX);
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u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL);
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u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA);
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u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY);
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len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
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len = (len > len_fpga) ? len : len_fpga;
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len = (len > len_delay) ? len : len_delay;
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u32 handoff_table[len];
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/* setup the pin sel */
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len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux : SOC64_HANDOFF_MUX_LEN;
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socfpga_handoff_read((void *)SOC64_HANDOFF_MUX, handoff_table, len);
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for (i = 0; i < len; i = i + 2) {
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writel(handoff_table[i + 1],
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handoff_table[i] +
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(u8 *)socfpga_get_sysmgr_addr() +
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SYSMGR_SOC64_PINSEL0);
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}
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/* setup the pin ctrl */
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len = (len_ioctl < SOC64_HANDOFF_IOCTL_LEN) ? len_ioctl : SOC64_HANDOFF_IOCTL_LEN;
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socfpga_handoff_read((void *)SOC64_HANDOFF_IOCTL, handoff_table, len);
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for (i = 0; i < len; i = i + 2) {
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writel(handoff_table[i + 1],
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handoff_table[i] +
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(u8 *)socfpga_get_sysmgr_addr() +
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SYSMGR_SOC64_IOCTRL0);
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}
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/* setup the fpga use */
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len = (len_fpga < SOC64_HANDOFF_FPGA_LEN) ? len_fpga : SOC64_HANDOFF_FPGA_LEN;
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socfpga_handoff_read((void *)SOC64_HANDOFF_FPGA, handoff_table, len);
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for (i = 0; i < len; i = i + 2) {
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writel(handoff_table[i + 1],
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handoff_table[i] +
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(u8 *)socfpga_get_sysmgr_addr() +
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SYSMGR_SOC64_EMAC0_USEFPGA);
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}
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/* setup the IO delay */
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len = (len_delay < SOC64_HANDOFF_DELAY_LEN) ? len_delay : SOC64_HANDOFF_DELAY_LEN;
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socfpga_handoff_read((void *)SOC64_HANDOFF_DELAY, handoff_table, len);
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for (i = 0; i < len; i = i + 2) {
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writel(handoff_table[i + 1],
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handoff_table[i] +
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(u8 *)socfpga_get_sysmgr_addr() +
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SYSMGR_SOC64_IODELAY0);
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}
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}
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