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5119cffaf4
Sub-device information is retrieved from the JTAG ID in Boot Scratch Cold 4 Register. This interface is introduced to allow device-specific errata workarounds to be applied in the future, based on the detected sub-device type. Signed-off-by: Tingting Meng <tingting.meng@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
144 lines
3.3 KiB
C
144 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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*
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*/
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#include <altera.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <log.h>
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#include <asm/arch/board.h>
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#include <asm/arch/mailbox_s10.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/global_data.h>
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#include <mach/clock_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Agilex5 Sub Device Jtag ID List */
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#define A3690_JTAG_ID 0x036090DD
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#define A3694_JTAG_ID 0x436090DD
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#define A36C0_JTAG_ID 0x0360C0DD
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#define A36C4_JTAG_ID 0x4360C0DD
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#define A36D0_JTAG_ID 0x0360D0DD
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#define A36D4_JTAG_ID 0x4360D0DD
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#define A36F0_JTAG_ID 0x0360F0DD
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#define A36F4_JTAG_ID 0x4360F0DD
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#define A3610_JTAG_ID 0x036010DD
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#define A3614_JTAG_ID 0x436010DD
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#define A3630_JTAG_ID 0x036030DD
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#define A3634_JTAG_ID 0x436030DD
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#define JTAG_ID_MASK 0xCFF0FFFF
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/*
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* FPGA programming support for SoC FPGA Stratix 10
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*/
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static Altera_desc altera_fpga[] = {
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{
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/* Family */
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Intel_FPGA_SDM_Mailbox,
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/* Interface type */
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secure_device_manager_mailbox,
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/* No limitation as additional data will be ignored */
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-1,
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/* No device function table */
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NULL,
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/* Base interface address specified in driver */
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NULL,
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/* No cookie implementation */
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0
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},
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};
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u32 socfpga_get_jtag_id(void)
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{
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u32 jtag_id;
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jtag_id = readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD4);
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if (!jtag_id) {
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debug("Failed to read JTAG ID. Default JTAG ID to A36F4_JTAG_ID.\n");
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jtag_id = A36F4_JTAG_ID;
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}
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debug("%s: jtag_id: 0x%x\n", __func__, jtag_id);
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return jtag_id;
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}
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/*
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* The Agilex5 platform has enabled the bloblist feature, and the bloblist
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* address and size are initialized based on the defconfig settings.
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* During the SPL phase, this function is used to prevent the bloblist
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* from initializing its address and size with the saved boot parameters,
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* which may have been incorrectly set.
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*/
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void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
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unsigned long r3)
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{
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save_boot_params_ret();
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}
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/*
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* Print CPU information
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*/
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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printf("CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n",
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IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53");
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return 0;
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}
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#endif
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#ifdef CONFIG_ARCH_MISC_INIT
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int arch_misc_init(void)
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{
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char qspi_string[13];
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unsigned long id;
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sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
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env_set("qspi_clock", qspi_string);
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/* Export board_id as environment variable */
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id = socfpga_get_board_id();
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env_set_ulong("board_id", id);
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return 0;
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}
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#endif
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int arch_early_init_r(void)
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{
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socfpga_fpga_add(&altera_fpga[0]);
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return 0;
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}
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/* Return 1 if FPGA is ready otherwise return 0 */
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int is_fpga_config_ready(void)
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{
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return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) &
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SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK;
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}
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void do_bridge_reset(int enable, unsigned int mask)
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{
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/* Check FPGA status before bridge enable */
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if (!is_fpga_config_ready()) {
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puts("FPGA not ready. Bridge reset aborted!\n");
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return;
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}
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socfpga_bridges_reset(enable, mask);
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}
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