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Agilex5 FPGA switch section in the handoff data is larger by 32 bytes than the default value as these extra sections contains I3C0 and I3C1 register offsets and values with 4 bytes each. This requires 4 more times of reading the FPGA switch section of the handoff data to fully populate the handoff data table in the memory during runtime. Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
114 lines
4.2 KiB
C
114 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
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* Copyright (C) 2025 Altera Corporation <www.altera.com>
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*
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*/
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#ifndef _HANDOFF_SOC64_H_
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#define _HANDOFF_SOC64_H_
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/*
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* Offset for HW handoff from Quartus tools
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*/
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/* HPS handoff */
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#define SOC64_HANDOFF_MAGIC_BOOT 0x424F4F54
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#define SOC64_HANDOFF_MAGIC_MUX 0x504D5558
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#define SOC64_HANDOFF_MAGIC_IOCTL 0x494F4354
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#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
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#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159
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#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53
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#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524D
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
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#define SOC64_HANDOFF_MAGIC_PERI 0x50455249
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#else
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#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343
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#endif
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#define SOC64_HANDOFF_OFFSET_LENGTH 0x4
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#define SOC64_HANDOFF_OFFSET_DATA 0x10
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#define SOC64_HANDOFF_SIZE 4096
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
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IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
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IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
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#define SOC64_HANDOFF_BASE 0xFFE3F000
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
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#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x634)
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/* DDR handoff */
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#define SOC64_HANDOFF_DDR_BASE (SOC64_HANDOFF_BASE + 0x610)
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#define SOC64_HANDOFF_DDR_LEN 5
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#define SOC64_HANDOFF_DDR_INTERLEAVING_MODE_MASK BIT(0)
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#define SOC64_HANDOFF_DDR_MEMORY_TYPE_MASK BIT(0)
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#else
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#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
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#endif
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#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
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#define SOC64_HANDOFF_BASE 0x0007F000
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#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
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#define SOC64_HANDOFF_BASE 0xFFE5F000
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#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630)
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/* DDR handoff */
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#define SOC64_HANDOFF_DDR_BASE 0xFFE5C000
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#define SOC64_HANDOFF_DDR_MAGIC 0x48524444
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#define SOC64_HANDOFF_DDR_UMCTL2_MAGIC 0x4C54434D
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#define SOC64_HANDOFF_DDR_UMCTL2_DDR4_TYPE 0x34524444
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#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_0_TYPE 0x3044504C
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#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_1_TYPE 0x3144504C
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#define SOC64_HANDOFF_DDR_MEMRESET_BASE (SOC64_HANDOFF_DDR_BASE + 0xC)
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#define SOC64_HANDOFF_DDR_UMCTL2_SECTION (SOC64_HANDOFF_DDR_BASE + 0x10)
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#define SOC64_HANDOFF_DDR_PHY_MAGIC 0x43594850
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#define SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC 0x45594850
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#define SOC64_HANDOFF_DDR_PHY_BASE_OFFSET 0x8
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#define SOC64_HANDOFF_DDR_UMCTL2_TYPE_OFFSET 0x8
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#define SOC64_HANDOFF_DDR_UMCTL2_BASE_ADDR_OFFSET 0xC
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#define SOC64_HANDOFF_DDR_TRAIN_IMEM_1D_SECTION 0xFFE50000
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#define SOC64_HANDOFF_DDR_TRAIN_DMEM_1D_SECTION 0xFFE58000
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#define SOC64_HANDOFF_DDR_TRAIN_IMEM_2D_SECTION 0xFFE44000
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#define SOC64_HANDOFF_DDR_TRAIN_DMEM_2D_SECTION 0xFFE4C000
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#define SOC64_HANDOFF_DDR_TRAIN_IMEM_LENGTH SZ_32K
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#define SOC64_HANDOFF_DDR_TRAIN_DMEM_LENGTH SZ_16K
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#endif
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#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
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#define SOC64_HANDOFF_IOCTL (SOC64_HANDOFF_BASE + 0x1A0)
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#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
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#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0)
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#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580)
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
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#define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620)
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#define SOC64_HANDOFF_PERI_LEN 1
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#define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634)
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#define SOC64_HANDOFF_SDRAM_LEN 5
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#endif
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
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#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608)
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#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C)
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#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
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#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x60c)
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#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x610)
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#else
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#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc)
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#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
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#endif
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#define SOC64_HANDOFF_MUX_LEN 96
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#define SOC64_HANDOFF_IOCTL_LEN 96
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
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#define SOC64_HANDOFF_FPGA_LEN 42
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#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
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#define SOC64_HANDOFF_FPGA_LEN 44
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#else
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#define SOC64_HANDOFF_FPGA_LEN 40
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#endif
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#define SOC64_HANDOFF_DELAY_LEN 96
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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int socfpga_get_handoff_size(void *handoff_address);
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int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len);
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#endif
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#endif /* _HANDOFF_SOC64_H_ */
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