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f9c4fd3871
- Add base addresses for WDG3, WDG4, GPIO6, and GPIO7 for i.MX94. - Introduce common.h with macros of clock IDs, power domains, and CPU types for platform-specific replacement (e.g., i.MX94, i.MX95). - Extend imx_get_mac_from_fuse() to support i.MX94. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
72 lines
1.4 KiB
C
72 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2025 NXP
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*/
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#include <asm/arch/clock.h>
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#include <dm/uclass.h>
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#include <scmi_agent.h>
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#include <scmi_nxp_protocols.h>
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#include "common.h"
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u32 get_arm_core_clk(void)
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{
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u32 val;
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val = imx_clk_scmi_get_rate(SCMI_CLK(SEL_A55C0));
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if (val)
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return val;
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return imx_clk_scmi_get_rate(SCMI_CLK(A55));
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}
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void init_uart_clk(u32 index)
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{
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u32 clock_id;
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switch (index) {
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case 0:
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clock_id = SCMI_CLK(LPUART1);
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break;
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case 1:
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clock_id = SCMI_CLK(LPUART2);
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break;
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case 2:
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clock_id = SCMI_CLK(LPUART3);
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break;
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default:
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return;
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}
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/* 24MHz */
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imx_clk_scmi_enable(clock_id, false);
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imx_clk_scmi_set_parent(clock_id, SCMI_CLK(24M));
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imx_clk_scmi_set_rate(clock_id, 24000000);
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imx_clk_scmi_enable(clock_id, true);
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}
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unsigned int mxc_get_clock(enum mxc_clock clk)
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{
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switch (clk) {
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case MXC_ARM_CLK:
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return get_arm_core_clk();
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case MXC_IPG_CLK:
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return imx_clk_scmi_get_rate(SCMI_CLK(BUSWAKEUP));
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case MXC_CSPI_CLK:
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return imx_clk_scmi_get_rate(SCMI_CLK(LPSPI1));
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case MXC_ESDHC_CLK:
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return imx_clk_scmi_get_rate(SCMI_CLK(USDHC1));
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case MXC_ESDHC2_CLK:
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return imx_clk_scmi_get_rate(SCMI_CLK(USDHC2));
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case MXC_ESDHC3_CLK:
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return imx_clk_scmi_get_rate(SCMI_CLK(USDHC3));
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case MXC_UART_CLK:
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return imx_clk_scmi_get_rate(SCMI_CLK(LPUART1));
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case MXC_FLEXSPI_CLK:
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return imx_clk_scmi_get_rate(SCMI_CLK(FLEXSPI1));
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default:
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return -1;
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};
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return -1;
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};
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