Jonas Karlman 0b6afc3993 clk: rockchip: rk356x: Fix set rate of SCLK_SFC clock ...

The SCLK_SFC can be set to a rate of 24, 50, 75, 100, 125 or 150 MHz.

However, clk_set_rate() will fail unless one of those exact rates are
used, and with newer and updated device tree files that contain
spi-max-frequency values that does not exactly match these rates use of
SPI flash may fail.

Fix this by using the highest possible rate that exceeds or is equal to
the requested rate.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

2024-04-26 15:47:04 +08:00

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clk_pll.c

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clk_px30.c

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clk_rk322x.c

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clk_rk3036.c

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clk_rk3066.c

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clk_rk3128.c

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clk_rk3188.c

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clk_rk3288.c

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clk_rk3308.c

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clk_rk3328.c

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clk_rk3368.c

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clk_rk3399.c

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clk_rk3568.c

clk: rockchip: rk356x: Fix set rate of SCLK_SFC clock

2024-04-26 15:47:04 +08:00

clk_rk3588.c

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clk_rv1108.c

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clk_rv1126.c

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Makefile

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