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50b371fd68
Add support of STM32MP13x Rev.Y for the Silicon revision REV_ID = 0x1003. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
139 lines
2.4 KiB
C
139 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright (C) 2022, STMicroelectronics - All Rights Reserved
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*/
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#define LOG_CATEGORY LOGC_ARCH
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#include <common.h>
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#include <log.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/sys_proto.h>
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/* SYSCFG register */
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#define SYSCFG_IDC_OFFSET 0x380
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#define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0)
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#define SYSCFG_IDC_DEV_ID_SHIFT 0
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#define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16)
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#define SYSCFG_IDC_REV_ID_SHIFT 16
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/* Device Part Number (RPN) = OTP_DATA1 lower 11 bits */
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#define RPN_SHIFT 0
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#define RPN_MASK GENMASK(11, 0)
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static u32 read_idc(void)
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{
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void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
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return readl(syscfg + SYSCFG_IDC_OFFSET);
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}
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u32 get_cpu_dev(void)
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{
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return (read_idc() & SYSCFG_IDC_DEV_ID_MASK) >> SYSCFG_IDC_DEV_ID_SHIFT;
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}
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u32 get_cpu_rev(void)
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{
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return (read_idc() & SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT;
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}
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/* Get Device Part Number (RPN) from OTP */
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static u32 get_cpu_rpn(void)
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{
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return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
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}
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u32 get_cpu_type(void)
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{
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return (get_cpu_dev() << 16) | get_cpu_rpn();
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}
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int get_eth_nb(void)
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{
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int nb_eth = 2;
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switch (get_cpu_type()) {
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case CPU_STM32MP131Dxx:
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fallthrough;
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case CPU_STM32MP131Cxx:
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fallthrough;
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case CPU_STM32MP131Axx:
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nb_eth = 1;
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break;
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default:
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nb_eth = 2;
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break;
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}
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return nb_eth;
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}
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void get_soc_name(char name[SOC_NAME_SIZE])
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{
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char *cpu_s, *cpu_r;
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/* MPUs Part Numbers */
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switch (get_cpu_type()) {
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case CPU_STM32MP135Fxx:
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cpu_s = "135F";
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break;
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case CPU_STM32MP135Dxx:
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cpu_s = "135D";
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break;
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case CPU_STM32MP135Cxx:
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cpu_s = "135C";
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break;
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case CPU_STM32MP135Axx:
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cpu_s = "135A";
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break;
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case CPU_STM32MP133Fxx:
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cpu_s = "133F";
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break;
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case CPU_STM32MP133Dxx:
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cpu_s = "133D";
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break;
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case CPU_STM32MP133Cxx:
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cpu_s = "133C";
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break;
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case CPU_STM32MP133Axx:
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cpu_s = "133A";
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break;
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case CPU_STM32MP131Fxx:
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cpu_s = "131F";
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break;
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case CPU_STM32MP131Dxx:
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cpu_s = "131D";
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break;
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case CPU_STM32MP131Cxx:
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cpu_s = "131C";
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break;
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case CPU_STM32MP131Axx:
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cpu_s = "131A";
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break;
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default:
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cpu_s = "????";
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break;
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}
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/* REVISION */
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switch (get_cpu_rev()) {
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case CPU_REV1:
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cpu_r = "A";
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break;
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case CPU_REV1_1:
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cpu_r = "Z";
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break;
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case CPU_REV1_2:
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cpu_r = "Y";
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break;
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default:
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cpu_r = "?";
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break;
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}
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snprintf(name, SOC_NAME_SIZE, "STM32MP%s Rev.%s", cpu_s, cpu_r);
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}
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