mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-10-26 05:51:29 +01:00
e0caa84ca6
Synchronise device tree with linux v5.19-rc5. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
616 lines
14 KiB
Plaintext
616 lines
14 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright 2019 NXP
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "imx8mp.dtsi"
|
|
|
|
/ {
|
|
model = "NXP i.MX8MPlus EVK board";
|
|
compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
|
|
|
|
chosen {
|
|
stdout-path = &uart2;
|
|
};
|
|
|
|
gpio-leds {
|
|
compatible = "gpio-leds";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_gpio_led>;
|
|
|
|
status {
|
|
label = "yellow:status";
|
|
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
|
|
default-state = "on";
|
|
};
|
|
};
|
|
|
|
memory@40000000 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x40000000 0 0xc0000000>,
|
|
<0x1 0x00000000 0 0xc0000000>;
|
|
};
|
|
|
|
reg_can1_stby: regulator-can1-stby {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "can1-stby";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_flexcan1_reg>;
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
|
|
reg_can2_stby: regulator-can2-stby {
|
|
compatible = "regulator-fixed";
|
|
regulator-name = "can2-stby";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_flexcan2_reg>;
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
|
|
reg_usdhc2_vmmc: regulator-usdhc2 {
|
|
compatible = "regulator-fixed";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
|
|
regulator-name = "VSD_3V3";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
|
|
enable-active-high;
|
|
};
|
|
};
|
|
|
|
&flexcan1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_flexcan1>;
|
|
xceiver-supply = <®_can1_stby>;
|
|
status = "okay";
|
|
};
|
|
|
|
&flexcan2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_flexcan2>;
|
|
xceiver-supply = <®_can2_stby>;
|
|
status = "disabled";/* can2 pin conflict with pdm */
|
|
};
|
|
|
|
&eqos {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_eqos>;
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <ðphy0>;
|
|
snps,force_thresh_dma_mode;
|
|
snps,mtl-tx-config = <&mtl_tx_setup>;
|
|
snps,mtl-rx-config = <&mtl_rx_setup>;
|
|
status = "okay";
|
|
|
|
mdio {
|
|
compatible = "snps,dwmac-mdio";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ethphy0: ethernet-phy@1 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <1>;
|
|
eee-broken-1000t;
|
|
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
|
|
reset-assert-us = <10000>;
|
|
reset-deassert-us = <80000>;
|
|
realtek,clkout-disable;
|
|
};
|
|
};
|
|
|
|
mtl_tx_setup: tx-queues-config {
|
|
snps,tx-queues-to-use = <5>;
|
|
snps,tx-sched-sp;
|
|
|
|
queue0 {
|
|
snps,dcb-algorithm;
|
|
snps,priority = <0x1>;
|
|
};
|
|
|
|
queue1 {
|
|
snps,dcb-algorithm;
|
|
snps,priority = <0x2>;
|
|
};
|
|
|
|
queue2 {
|
|
snps,dcb-algorithm;
|
|
snps,priority = <0x4>;
|
|
};
|
|
|
|
queue3 {
|
|
snps,dcb-algorithm;
|
|
snps,priority = <0x8>;
|
|
};
|
|
|
|
queue4 {
|
|
snps,dcb-algorithm;
|
|
snps,priority = <0xf0>;
|
|
};
|
|
};
|
|
|
|
mtl_rx_setup: rx-queues-config {
|
|
snps,rx-queues-to-use = <5>;
|
|
snps,rx-sched-sp;
|
|
|
|
queue0 {
|
|
snps,dcb-algorithm;
|
|
snps,priority = <0x1>;
|
|
snps,map-to-dma-channel = <0>;
|
|
};
|
|
|
|
queue1 {
|
|
snps,dcb-algorithm;
|
|
snps,priority = <0x2>;
|
|
snps,map-to-dma-channel = <1>;
|
|
};
|
|
|
|
queue2 {
|
|
snps,dcb-algorithm;
|
|
snps,priority = <0x4>;
|
|
snps,map-to-dma-channel = <2>;
|
|
};
|
|
|
|
queue3 {
|
|
snps,dcb-algorithm;
|
|
snps,priority = <0x8>;
|
|
snps,map-to-dma-channel = <3>;
|
|
};
|
|
|
|
queue4 {
|
|
snps,dcb-algorithm;
|
|
snps,priority = <0xf0>;
|
|
snps,map-to-dma-channel = <4>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&fec {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_fec>;
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <ðphy1>;
|
|
fsl,magic-packet;
|
|
status = "okay";
|
|
|
|
mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ethphy1: ethernet-phy@1 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
reg = <1>;
|
|
eee-broken-1000t;
|
|
reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
|
|
reset-assert-us = <10000>;
|
|
reset-deassert-us = <80000>;
|
|
realtek,clkout-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c1 {
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1>;
|
|
status = "okay";
|
|
|
|
pmic@25 {
|
|
compatible = "nxp,pca9450c";
|
|
reg = <0x25>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pmic>;
|
|
interrupt-parent = <&gpio1>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
|
|
|
|
regulators {
|
|
BUCK1 {
|
|
regulator-name = "BUCK1";
|
|
regulator-min-microvolt = <720000>;
|
|
regulator-max-microvolt = <1000000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-ramp-delay = <3125>;
|
|
};
|
|
|
|
BUCK2 {
|
|
regulator-name = "BUCK2";
|
|
regulator-min-microvolt = <720000>;
|
|
regulator-max-microvolt = <1025000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
regulator-ramp-delay = <3125>;
|
|
nxp,dvs-run-voltage = <950000>;
|
|
nxp,dvs-standby-voltage = <850000>;
|
|
};
|
|
|
|
BUCK4 {
|
|
regulator-name = "BUCK4";
|
|
regulator-min-microvolt = <3000000>;
|
|
regulator-max-microvolt = <3600000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
BUCK5 {
|
|
regulator-name = "BUCK5";
|
|
regulator-min-microvolt = <1650000>;
|
|
regulator-max-microvolt = <1950000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
BUCK6 {
|
|
regulator-name = "BUCK6";
|
|
regulator-min-microvolt = <1045000>;
|
|
regulator-max-microvolt = <1155000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
LDO1 {
|
|
regulator-name = "LDO1";
|
|
regulator-min-microvolt = <1650000>;
|
|
regulator-max-microvolt = <1950000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
LDO3 {
|
|
regulator-name = "LDO3";
|
|
regulator-min-microvolt = <1710000>;
|
|
regulator-max-microvolt = <1890000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
LDO5 {
|
|
regulator-name = "LDO5";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&i2c3 {
|
|
clock-frequency = <400000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c3>;
|
|
status = "okay";
|
|
|
|
pca6416: gpio@20 {
|
|
compatible = "ti,tca6416";
|
|
reg = <0x20>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_pca6416_int>;
|
|
interrupt-parent = <&gpio1>;
|
|
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
|
|
gpio-line-names = "EXT_PWREN1",
|
|
"EXT_PWREN2",
|
|
"CAN1/I2C5_SEL",
|
|
"PDM/CAN2_SEL",
|
|
"FAN_EN",
|
|
"PWR_MEAS_IO1",
|
|
"PWR_MEAS_IO2",
|
|
"EXP_P0_7",
|
|
"EXP_P1_0",
|
|
"EXP_P1_1",
|
|
"EXP_P1_2",
|
|
"EXP_P1_3",
|
|
"EXP_P1_4",
|
|
"EXP_P1_5",
|
|
"EXP_P1_6",
|
|
"EXP_P1_7";
|
|
};
|
|
};
|
|
|
|
/* I2C on expansion connector J22. */
|
|
&i2c5 {
|
|
clock-frequency = <100000>; /* Lower clock speed for external bus. */
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c5>;
|
|
status = "disabled"; /* can1 pins conflict with i2c5 */
|
|
|
|
/* GPIO 2 of PCA6416 is used to switch between CAN1 and I2C5 functions:
|
|
* LOW: CAN1 (default, pull-down)
|
|
* HIGH: I2C5
|
|
* You need to set it to high to enable I2C5 (for example, add gpio-hog
|
|
* in pca6416 node).
|
|
*/
|
|
};
|
|
|
|
&snvs_pwrkey {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart2 {
|
|
/* console */
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usb3_phy1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb3_1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usb_dwc3_1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb1_vbus>;
|
|
dr_mode = "host";
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc2 {
|
|
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
|
|
assigned-clock-rates = <400000000>;
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
|
|
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
|
|
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
|
|
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
|
|
vmmc-supply = <®_usdhc2_vmmc>;
|
|
bus-width = <4>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc3 {
|
|
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
|
|
assigned-clock-rates = <400000000>;
|
|
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
|
pinctrl-0 = <&pinctrl_usdhc3>;
|
|
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
|
|
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
|
|
bus-width = <8>;
|
|
non-removable;
|
|
status = "okay";
|
|
};
|
|
|
|
&wdog1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_wdog>;
|
|
fsl,ext-reset-output;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl_eqos: eqosgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
|
|
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
|
|
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
|
|
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
|
|
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
|
|
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
|
|
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
|
|
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
|
|
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
|
|
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
|
|
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
|
|
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
|
|
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
|
|
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
|
|
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_fec: fecgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
|
|
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
|
|
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
|
|
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
|
|
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
|
|
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
|
|
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
|
|
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
|
|
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
|
|
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
|
|
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan1: flexcan1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
|
|
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan2: flexcan2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
|
|
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan1_reg: flexcan1reggrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
|
|
>;
|
|
};
|
|
|
|
pinctrl_flexcan2_reg: flexcan2reggrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
|
|
>;
|
|
};
|
|
|
|
pinctrl_gpio_led: gpioledgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
|
|
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3
|
|
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c5: i2c5grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3
|
|
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_pmic: pmicgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x000001c0
|
|
>;
|
|
};
|
|
|
|
pinctrl_pca6416_int: pca6416_int_grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* Input pull-up. */
|
|
>;
|
|
};
|
|
|
|
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
|
|
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
|
|
>;
|
|
};
|
|
|
|
pinctrl_usb1_vbus: usb1grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
|
|
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
|
|
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
|
|
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3: usdhc3grp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
|
>;
|
|
};
|
|
|
|
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
|
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
|
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
|
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
|
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
|
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
|
>;
|
|
};
|
|
|
|
pinctrl_wdog: wdoggrp {
|
|
fsl,pins = <
|
|
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
|
|
>;
|
|
};
|
|
};
|