mirror of
https://source.denx.de/u-boot/u-boot.git
synced 2025-11-04 10:21:25 +01:00
54a08c4139
This syncs drivers/ddr/marvell/a38x/ with the master branch of repository
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
up to the commit "mv_ddr: a3700: Use the right size for memset to not overflow"
d5acc10c287e40cc2feeb28710b92e45c93c702c
This patch was created by following steps:
1. Replace all a38x files in U-Boot tree by files from upstream github
Marvell mv-ddr-marvell repository.
2. Run following command to omit portions not relevant for a38x, ddr3, and ddr4:
files=drivers/ddr/marvell/a38x/*
unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_APN806 \
-UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \
-UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \
-UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DCONFIG_ARMADA_38X -UCONFIG_ARMADA_39X \
-UCONFIG_64BIT $files
3. Manually change license to SPDX-License-Identifier
(upstream license in upstream github repository contains long license
texts and U-Boot is using just SPDX-License-Identifier.
After applying this patch, a38x, ddr3, and ddr4 code in upstream Marvell github
repository and in U-Boot would be fully identical. So in future applying
above steps could be used to sync code again.
The only change in this patch are:
1. Some fixes with include files.
2. Some function return and basic type defines changes in
mv_ddr_plat.c (to correct Marvell bug).
3. Remove of dead code in newly copied files (as a result of the
filter script stripping out everything other than a38x, dd3, and ddr4).
Reference:
"ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repository"
107c3391b9
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
164 lines
3.8 KiB
C
164 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#ifndef _DDR3_TRAINING_IP_H_
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#define _DDR3_TRAINING_IP_H_
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#include "ddr_topology_def.h"
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#define TIP_ENG_LOCK 0x02000000
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#define TIP_TX_DLL_RANGE_MAX 64
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#define GET_MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2)
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#define GET_MAX(arg1, arg2) ((arg1) < (arg2)) ? (arg2) : (arg1)
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#define INIT_CONTROLLER_MASK_BIT 0x00000001
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#define STATIC_LEVELING_MASK_BIT 0x00000002
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#define SET_LOW_FREQ_MASK_BIT 0x00000004
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#define LOAD_PATTERN_MASK_BIT 0x00000008
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#define SET_MEDIUM_FREQ_MASK_BIT 0x00000010
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#define WRITE_LEVELING_MASK_BIT 0x00000020
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#define LOAD_PATTERN_2_MASK_BIT 0x00000040
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#define READ_LEVELING_MASK_BIT 0x00000080
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#define SW_READ_LEVELING_MASK_BIT 0x00000100
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#define WRITE_LEVELING_SUPP_MASK_BIT 0x00000200
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#define PBS_RX_MASK_BIT 0x00000400
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#define PBS_TX_MASK_BIT 0x00000800
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#define SET_TARGET_FREQ_MASK_BIT 0x00001000
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#define ADJUST_DQS_MASK_BIT 0x00002000
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#define WRITE_LEVELING_TF_MASK_BIT 0x00004000
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#define LOAD_PATTERN_HIGH_MASK_BIT 0x00008000
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#define READ_LEVELING_TF_MASK_BIT 0x00010000
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#define WRITE_LEVELING_SUPP_TF_MASK_BIT 0x00020000
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#define DM_PBS_TX_MASK_BIT 0x00040000
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#define RL_DQS_BURST_MASK_BIT 0x00080000
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#define CENTRALIZATION_RX_MASK_BIT 0x00100000
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#define CENTRALIZATION_TX_MASK_BIT 0x00200000
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#define TX_EMPHASIS_MASK_BIT 0x00400000
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#define PER_BIT_READ_LEVELING_TF_MASK_BIT 0x00800000
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#define VREF_CALIBRATION_MASK_BIT 0x01000000
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#define WRITE_LEVELING_LF_MASK_BIT 0x02000000
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/* DDR4 Specific Training Mask bits */
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#if defined (CONFIG_DDR4)
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#define RECEIVER_CALIBRATION_MASK_BIT 0x04000000
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#define WL_PHASE_CORRECTION_MASK_BIT 0x08000000
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#define DQ_VREF_CALIBRATION_MASK_BIT 0x10000000
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#define DQ_MAPPING_MASK_BIT 0x20000000
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#define DM_TUNING_MASK_BIT 0x40000000
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#endif /* CONFIG_DDR4 */
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enum hws_result {
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TEST_FAILED = 0,
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TEST_SUCCESS = 1,
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NO_TEST_DONE = 2
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};
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enum hws_training_result {
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RESULT_PER_BIT,
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RESULT_PER_BYTE
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};
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enum auto_tune_stage {
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INIT_CONTROLLER,
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STATIC_LEVELING,
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SET_LOW_FREQ,
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LOAD_PATTERN,
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SET_MEDIUM_FREQ,
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WRITE_LEVELING,
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LOAD_PATTERN_2,
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READ_LEVELING,
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#if defined(CONFIG_DDR4)
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SW_READ_LEVELING,
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#endif /* CONFIG_DDR4 */
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WRITE_LEVELING_SUPP,
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PBS_RX,
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PBS_TX,
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SET_TARGET_FREQ,
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ADJUST_DQS,
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WRITE_LEVELING_TF,
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READ_LEVELING_TF,
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WRITE_LEVELING_SUPP_TF,
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DM_PBS_TX,
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VREF_CALIBRATION,
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CENTRALIZATION_RX,
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CENTRALIZATION_TX,
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TX_EMPHASIS,
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LOAD_PATTERN_HIGH,
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PER_BIT_READ_LEVELING_TF,
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#if defined(CONFIG_DDR4)
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RECEIVER_CALIBRATION,
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WL_PHASE_CORRECTION,
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DQ_VREF_CALIBRATION,
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DM_TUNING,
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DQ_MAPPING,
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#endif /* CONFIG_DDR4 */
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WRITE_LEVELING_LF,
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MAX_STAGE_LIMIT
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};
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enum hws_access_type {
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ACCESS_TYPE_UNICAST = 0,
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ACCESS_TYPE_MULTICAST = 1
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};
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enum hws_algo_type {
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ALGO_TYPE_DYNAMIC,
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ALGO_TYPE_STATIC
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};
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struct init_cntr_param {
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int is_ctrl64_bit;
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int do_mrs_phy;
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int init_phy;
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int msys_init;
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};
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struct pattern_info {
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u8 num_of_phases_tx;
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u8 tx_burst_size;
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u8 delay_between_bursts;
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u8 num_of_phases_rx;
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u32 start_addr;
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u8 pattern_len;
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};
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struct cs_element {
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u8 cs_num;
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u8 num_of_cs;
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};
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struct hws_tip_freq_config_info {
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u8 is_supported;
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u8 bw_per_freq;
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u8 rate_per_freq;
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};
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struct hws_cs_config_info {
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u32 cs_reg_value;
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u32 cs_cbe_value;
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};
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struct dfx_access {
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u8 pipe;
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u8 client;
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};
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struct hws_xsb_info {
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struct dfx_access *dfx_table;
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};
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int ddr3_tip_register_dq_table(u32 dev_num, u32 *table);
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int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
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int hws_ddr3_tip_init_controller(u32 dev_num,
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struct init_cntr_param *init_cntr_prm);
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int hws_ddr3_tip_load_topology_map(u32 dev_num,
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struct mv_ddr_topology_map *topology);
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int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
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int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
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u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
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u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
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#endif /* _DDR3_TRAINING_IP_H_ */
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