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u-boot/arch/riscv
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Yixun Lan 4416f07940 riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board 
Only add basic support for CPU, PLIC UART and Timer.

Reviewed-by: Wei Fu <wefu@redhat.com>
Signed-off-by: Yixun Lan <dlan@gentoo.org>
2023-07-12 13:21:41 +08:00
..
cpu
riscv: Rename SiFive CLINT to RISC-V ALINT
2023-07-12 13:21:40 +08:00
dts
riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board
2023-07-12 13:21:41 +08:00
include/asm
riscv: Rename SiFive CLINT to RISC-V ALINT
2023-07-12 13:21:40 +08:00
lib
riscv: Rename SiFive CLINT to RISC-V ALINT
2023-07-12 13:21:40 +08:00
config.mk
riscv: Support CONFIG_REMAKE_ELF
2023-04-20 20:45:08 +08:00
Kconfig
riscv: t-head: licheepi4a: initial support added
2023-07-12 13:21:41 +08:00
Makefile
riscv: support building double-float modules
2022-10-20 15:22:21 +08:00